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| author | Albert Magyar | 2020-07-20 12:11:44 -0700 |
|---|---|---|
| committer | Albert Magyar | 2020-07-21 13:06:53 -0700 |
| commit | 7e9f424fb7dcd11c894ceb9f6f049fd9eda80632 (patch) | |
| tree | 1fa15e357d0af7b82316fa2ee659e2e98118488c /src/test/scala/chiselTests/PrintableSpec.scala | |
| parent | 4a0e828cfe76e0d3bd6c4a0cc593589fe74ed0ba (diff) | |
Delete outdated scalastyle configuration comments from source
Diffstat (limited to 'src/test/scala/chiselTests/PrintableSpec.scala')
| -rw-r--r-- | src/test/scala/chiselTests/PrintableSpec.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/PrintableSpec.scala b/src/test/scala/chiselTests/PrintableSpec.scala index 8e39d405..2ac2ad5d 100644 --- a/src/test/scala/chiselTests/PrintableSpec.scala +++ b/src/test/scala/chiselTests/PrintableSpec.scala @@ -128,7 +128,7 @@ class PrintableSpec extends AnyFlatSpec with Matchers { printf(p"${FullName(myInst.io.fizz)}") } val firrtl = (new ChiselStage).emitChirrtl(new MyModule) - println(firrtl) // scalastyle:ignore regex + println(firrtl) getPrintfs(firrtl) match { case Seq(Printf("foo", Seq()), Printf("myWire.foo", Seq()), |