Add ChiselPhase, Stop writing files in ChiselStage$ methods, Expand ChiselStage$ helpers (#1566)

* Add ChiselPhase

* Use ChiselPhase in ChiselStage, remove targets

Switch from a one-off PhaseManager inside ChiselStage to actually
using the newly added ChiselPhase. This removes the targets
method (and API) from ChiselStage.

* Stop writing to files in ChiselStage$ methods

Change the ChiselStage companion object methods, elaborate and
convert, to not write files. Under the hood, these are switched from
using ChiselStage (which, like all phases, will write files) to using
ChiselPhase.

* Test that ChiselStage$ methods write no files

Modify existing ChiselStage object method tests to check that no files
are written.

* Expand ChiselStage$ API with more helpers

This adds additional methods to the ChiselStage object for going
directly from a Chisel module to a string including: CHIRRTL, high
FIRRTL IR, Verilog, and SystemVerilog.

Differing from their ChiselStage class counterparts, these take no
arguments other than the module and write no files.

* Add tests of new ChiselStage$ helper methods

* Use ChiselStage object in tests

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

1 files changed, 12 insertions, 12 deletions

diff --git a/src/test/scala/chiselTests/PrintableSpec.scala b/src/test/scala/chiselTests/PrintableSpec.scala
index 2ac2ad5d..283af640 100644
--- a/src/test/scala/chiselTests/PrintableSpec.scala
+++ b/src/test/scala/chiselTests/PrintableSpec.scala
@@ -38,7 +38,7 @@ class PrintableSpec extends AnyFlatSpec with Matchers {
     class MyModule extends BasicTester {
       printf(p"An exact string")
     }
-    val firrtl = (new ChiselStage).emitChirrtl(new MyModule)
+    val firrtl = ChiselStage.emitChirrtl(new MyModule)
     getPrintfs(firrtl) match {
       case Seq(Printf("An exact string", Seq())) =>
       case e => fail()
@@ -48,7 +48,7 @@ class PrintableSpec extends AnyFlatSpec with Matchers {
     class MyModule extends BasicTester {
       printf(p"First " + PString("Second ") + "Third")
     }
-    val firrtl = (new ChiselStage).emitChirrtl(new MyModule)
+    val firrtl = ChiselStage.emitChirrtl(new MyModule)
     getPrintfs(firrtl) match {
       case Seq(Printf("First Second Third", Seq())) =>
       case e => fail()
@@ -59,7 +59,7 @@ class PrintableSpec extends AnyFlatSpec with Matchers {
       val myInt = 1234
       printf(p"myInt = $myInt")
     }
-    val firrtl = (new ChiselStage).emitChirrtl(new MyModule)
+    val firrtl = ChiselStage.emitChirrtl(new MyModule)
     getPrintfs(firrtl) match {
       case Seq(Printf("myInt = 1234", Seq())) =>
       case e => fail()
@@ -70,7 +70,7 @@ class PrintableSpec extends AnyFlatSpec with Matchers {
       val myWire = WireDefault(1234.U)
       printf(p"myWire = ${Decimal(myWire)}")
     }
-    val firrtl = (new ChiselStage).emitChirrtl(new MyModule)
+    val firrtl = ChiselStage.emitChirrtl(new MyModule)
     getPrintfs(firrtl) match {
       case Seq(Printf("myWire = %d", Seq("myWire"))) =>
       case e => fail()
@@ -80,7 +80,7 @@ class PrintableSpec extends AnyFlatSpec with Matchers {
     class MyModule extends BasicTester {
       printf(Decimal(10.U(32.W)))
     }
-    val firrtl = (new ChiselStage).emitChirrtl(new MyModule)
+    val firrtl = ChiselStage.emitChirrtl(new MyModule)
     getPrintfs(firrtl) match {
       case Seq(Printf("%d", Seq(lit))) =>
         assert(lit contains "UInt<32>")
@@ -91,7 +91,7 @@ class PrintableSpec extends AnyFlatSpec with Matchers {
     class MyModule extends BasicTester {
       printf(p"%")
     }
-    val firrtl = (new ChiselStage).emitChirrtl(new MyModule)
+    val firrtl = ChiselStage.emitChirrtl(new MyModule)
     getPrintfs(firrtl) match {
       case Seq(Printf("%%", Seq())) =>
       case e => fail()
@@ -101,7 +101,7 @@ class PrintableSpec extends AnyFlatSpec with Matchers {
     class MyModule extends BasicTester {
       printf(p"\t")
     }
-    val firrtl = (new ChiselStage).emitChirrtl(new MyModule)
+    val firrtl = ChiselStage.emitChirrtl(new MyModule)
     getPrintfs(firrtl) match {
       case Seq(Printf("\\t", Seq())) =>
       case e => fail()
@@ -127,7 +127,7 @@ class PrintableSpec extends AnyFlatSpec with Matchers {
       printf(p"${FullName(myWire.foo)}")
       printf(p"${FullName(myInst.io.fizz)}")
     }
-    val firrtl = (new ChiselStage).emitChirrtl(new MyModule)
+    val firrtl = ChiselStage.emitChirrtl(new MyModule)
     println(firrtl)
     getPrintfs(firrtl) match {
       case Seq(Printf("foo", Seq()),
@@ -146,7 +146,7 @@ class PrintableSpec extends AnyFlatSpec with Matchers {
       val myInst = Module(new MySubModule)
       printf(p"${myInst.io.fizz}")
     }
-    val firrtl = (new ChiselStage).emitChirrtl(new MyModule)
+    val firrtl = ChiselStage.emitChirrtl(new MyModule)
     getPrintfs(firrtl) match {
       case Seq(Printf("%d", Seq("myInst.io.fizz"))) =>
       case e => fail()
@@ -158,7 +158,7 @@ class PrintableSpec extends AnyFlatSpec with Matchers {
       val mySInt = WireDefault(-1.S)
       printf(p"$myUInt & $mySInt")
     }
-    val firrtl = (new ChiselStage).emitChirrtl(new MyModule)
+    val firrtl = ChiselStage.emitChirrtl(new MyModule)
     getPrintfs(firrtl) match {
       case Seq(Printf("%d & %d", Seq("myUInt", "mySInt"))) =>
       case e => fail()
@@ -170,7 +170,7 @@ class PrintableSpec extends AnyFlatSpec with Matchers {
       myVec foreach (_ := 0.U)
       printf(p"$myVec")
     }
-    val firrtl = (new ChiselStage).emitChirrtl(new MyModule)
+    val firrtl = ChiselStage.emitChirrtl(new MyModule)
     getPrintfs(firrtl) match {
       case Seq(Printf("Vec(%d, %d, %d, %d)",
                Seq("myVec[0]", "myVec[1]", "myVec[2]", "myVec[3]"))) =>
@@ -187,7 +187,7 @@ class PrintableSpec extends AnyFlatSpec with Matchers {
       myBun.bar := 0.U
       printf(p"$myBun")
     }
-    val firrtl = (new ChiselStage).emitChirrtl(new MyModule)
+    val firrtl = ChiselStage.emitChirrtl(new MyModule)
     getPrintfs(firrtl) match {
       case Seq(Printf("AnonymousBundle(foo -> %d, bar -> %d)",
                Seq("myBun.foo", "myBun.bar"))) =>