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authorMartin Schoeberl2019-01-25 23:24:01 -0800
committerRichard Lin2019-01-25 23:24:01 -0800
commit5509cdd4c8332c53151e10ba5bdbe0684af1c05b (patch)
tree15f4a7e8f83e0d249918bbce4198160fb2c5360f /src/test/scala/chiselTests/PrintableSpec.scala
parent4f5ec211cb59f9da37dbe91d0dfcb93c4d3d84c9 (diff)
WireDefault instead of WireInit, keep WireInit around (#986)
Diffstat (limited to 'src/test/scala/chiselTests/PrintableSpec.scala')
-rw-r--r--src/test/scala/chiselTests/PrintableSpec.scala6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/test/scala/chiselTests/PrintableSpec.scala b/src/test/scala/chiselTests/PrintableSpec.scala
index 6d74fbc0..6ae38a24 100644
--- a/src/test/scala/chiselTests/PrintableSpec.scala
+++ b/src/test/scala/chiselTests/PrintableSpec.scala
@@ -65,7 +65,7 @@ class PrintableSpec extends FlatSpec with Matchers {
}
it should "generate proper printf for simple Decimal printing" in {
class MyModule extends BasicTester {
- val myWire = WireInit(1234.U)
+ val myWire = WireDefault(1234.U)
printf(p"myWire = ${Decimal(myWire)}")
}
val firrtl = Driver.emit(() => new MyModule)
@@ -142,8 +142,8 @@ class PrintableSpec extends FlatSpec with Matchers {
}
it should "print UInts and SInts as Decimal by default" in {
class MyModule extends BasicTester {
- val myUInt = WireInit(0.U)
- val mySInt = WireInit(-1.S)
+ val myUInt = WireDefault(0.U)
+ val mySInt = WireDefault(-1.S)
printf(p"$myUInt & $mySInt")
}
val firrtl = Driver.emit(() => new MyModule)