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authorRichard Lin2017-08-17 17:24:02 -0700
committerJack Koenig2017-08-17 17:24:02 -0700
commit6e12ed9fd7a771eb30f44b8e1c4ab33f6ad8e0a6 (patch)
tree0ff452193d515adc32ecccacb2b58daa9a1d95cb /src/test/scala/chiselTests/PrintableSpec.scala
parent802cfc4405c28ae212a955a92c7a6ad2d2b6f0c2 (diff)
More of the bindings refactor (#635)
Rest of the binding refactor
Diffstat (limited to 'src/test/scala/chiselTests/PrintableSpec.scala')
-rw-r--r--src/test/scala/chiselTests/PrintableSpec.scala6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/test/scala/chiselTests/PrintableSpec.scala b/src/test/scala/chiselTests/PrintableSpec.scala
index 5f58429e..d733ab8c 100644
--- a/src/test/scala/chiselTests/PrintableSpec.scala
+++ b/src/test/scala/chiselTests/PrintableSpec.scala
@@ -67,7 +67,7 @@ class PrintableSpec extends FlatSpec with Matchers {
}
it should "generate proper printf for simple Decimal printing" in {
class MyModule extends BasicTester {
- val myWire = Wire(init = 1234.U)
+ val myWire = WireInit(1234.U)
printf(p"myWire = ${Decimal(myWire)}")
}
val firrtl = Driver.emit(() => new MyModule)
@@ -144,8 +144,8 @@ class PrintableSpec extends FlatSpec with Matchers {
}
it should "print UInts and SInts as Decimal by default" in {
class MyModule extends BasicTester {
- val myUInt = Wire(init = 0.U)
- val mySInt = Wire(init = -1.S)
+ val myUInt = WireInit(0.U)
+ val mySInt = WireInit(-1.S)
printf(p"$myUInt & $mySInt")
}
val firrtl = Driver.emit(() => new MyModule)