| Age | Commit message (Expand) | Author |
|---|
| 2019-10-21 | Fix BoringUtils.bore for internal boring | Schuyler Eldridge |
| 2019-09-13 | Add requirements to Queue class (#1176) | Jack Koenig |
| 2019-09-13 | Fix Queue.apply for size 0 in chisel3._ code (#1177) | Jack Koenig |
| 2019-09-11 | Move dontTouch, RawModule, and MultiIOModule out of experimental (#1162) | Jim Lawson |
| 2019-08-06 | Avoid when(reset) construct in LFSR | Andrew Waterman |
| 2019-08-01 | Remove anything deprecated since before 3.2 | Schuyler Eldridge |
| 2019-07-31 | Fix deprecated Vec usage in chisel3.util.LFSR16 | Schuyler Eldridge |
| 2019-07-18 | Add width utility functions to avoid incorrect usage of bare log2Ceil(). (#819) | Jim Lawson |
| 2019-06-11 | Added documentation to Decoupled, Conditionals, Counter (#1015) | Adam Izraelevitz |
| 2019-05-20 | Repackagecore rebase (#1078) | Jim Lawson |
| 2019-05-13 | Fix miscellaneous Scaladoc warnings | Schuyler Eldridge |
| 2019-05-12 | Cleanup loadMemoryFromFile documentation | Schuyler Eldridge |
| 2019-05-10 | Change LFSR16 deprecation from 3.3 -> 3.2 | Schuyler Eldridge |
| 2019-05-10 | Fix LFSR regression | Andrew Waterman |
| 2019-05-09 | PRNG state UInt->Vec[Bool], make async reset safe | Schuyler Eldridge |
| 2019-05-09 | Deprecate LFSR16, use FibonacciLFSR internally | Schuyler Eldridge |
| 2019-05-09 | Add chisel3.util.random lib w/ LFSR generator | Schuyler Eldridge |
| 2019-03-21 | Remove @chiselName from MixedVec (#1045) | Richard Lin |
| 2019-03-18 | Split #974 into two PRs - scalastyle updates (#1037) | Jim Lawson |
| 2019-03-15 | Use TransitName for improved Pipe naming (#1024) | Schuyler Eldridge |
| 2019-03-14 | Decouple implementation details from LoadMemoryAnnotation. (#1034) | Jim Lawson |
| 2019-03-11 | ScalaDocs improvement for utils Math, MixedVec (#1019) | Richard Lin |
| 2019-02-25 | Docs for ListLookup (#1028) | Richard Lin |
| 2019-02-19 | Add HasBlackBoxPath to BlackBoxUtils.scala (#903) | Albert Chen |
| 2019-02-19 | ScalaDoc for Mux (examples added) (#1014) | Martin Schoeberl |
| 2019-02-19 | Add Scaladoc for chisel3.util.TransitName | Schuyler Eldridge |
| 2019-02-19 | Util doc lsfr (#1021) | Chick Markley |
| 2019-02-19 | Documentation for Reg utilities (#1018) | Martin Schoeberl |
| 2019-02-19 | ScalaDoc for OneHot (#1016) | Martin Schoeberl |
| 2019-02-18 | Add requirement that Pipe latency >= 0 | Schuyler Eldridge |
| 2019-02-18 | Add Scaladoc for chisel3.util.Pipe | Schuyler Eldridge |
| 2019-02-18 | Add Scaldoc for chisel3.util.Valid | Schuyler Eldridge |
| 2019-01-25 | WireDefault instead of WireInit, keep WireInit around (#986) | Martin Schoeberl |
| 2019-01-22 | Changes to BoringUtils Scaladoc, paramater name | Schuyler Eldridge |
| 2019-01-22 | Fix BoringUtils deduplication bug | Schuyler Eldridge |
| 2019-01-21 | Unify internal (chisel3.core) and external (chisel3 / chisel3.experimental) M... | Richard Lin |
| 2018-12-04 | Add asBool, deprecate toBool | Jack Koenig |
| 2018-12-04 | Add asBools, deprecate toBools | Jack Koenig |
| 2018-11-02 | Fix Queue.io.count when entries=1 (#918) | Andrew Waterman |
| 2018-10-29 | Fix LoadMemoryTransform for Instance Annotations (#914) | Schuyler Eldridge |
| 2018-10-12 | Strong enums (#892) | Hasan Genc |
| 2018-10-03 | Modify ReadyValidIO noenq to set the data payload to DontCare. (#902) | Steve Burns |
| 2018-09-07 | Put do_* methods in SourceInfoTransformMacro group | Schuyler Eldridge |
| 2018-08-31 | Support for verilog memory loading. (#840) | Chick Markley |
| 2018-08-23 | Add FlattenInstance API | Schuyler Eldridge |
| 2018-08-23 | Add InlineInstance API | Schuyler Eldridge |
| 2018-08-22 | Implement varargs MixedVec API | Edward Wang |
| 2018-08-22 | Make MixedVec wire init consistent with VecInit | Edward Wang |
| 2018-08-22 | Remove dynamic indexing for now | Edward Wang |
| 2018-08-22 | MixedVec: clarify dynamic indexing of heterogeneous elements | Edward Wang |
