diff options
| author | Edward Wang | 2018-07-30 14:06:01 -0400 |
|---|---|---|
| committer | edwardcwang | 2018-08-22 11:55:38 -0700 |
| commit | cbad7ea20cd0b5ab7d4dc9d631350e1bc1555ddf (patch) | |
| tree | 26f26a4186edacf18ce9c3426c57dd188767d0c5 /src/main/scala/chisel3/util | |
| parent | c3c3cb6decac5ea196835d9bd2d26132cc81b51b (diff) | |
Remove dynamic indexing for now
We can sometimes shim with other workarounds like VecInit or manually
creating a mux
Diffstat (limited to 'src/main/scala/chisel3/util')
| -rw-r--r-- | src/main/scala/chisel3/util/MixedVec.scala | 19 |
1 files changed, 0 insertions, 19 deletions
diff --git a/src/main/scala/chisel3/util/MixedVec.scala b/src/main/scala/chisel3/util/MixedVec.scala index eeac76ea..30e5bde8 100644 --- a/src/main/scala/chisel3/util/MixedVec.scala +++ b/src/main/scala/chisel3/util/MixedVec.scala @@ -75,25 +75,6 @@ final class MixedVec[T <: Data](private val eltsIn: Seq[T]) extends Record with */ def apply(index: Int): T = elts(index) - /** - * Dynamically (via a mux) retrieve the element at the given index. - * This is implemented via a mux with the width of the widest element in this MixedVec. - * For example, a MixedVec of type Seq(UInt(4.W), UInt(8.W)) will create an 8-bit mux for this operation. - * Note: it is up to the user to process the resultant UInt (e.g. unflatten, etc). - * - * @param index Index to retrieve. If the index is out of range, it will return the first element. - * @return Retrieved index as a UInt with the width of the widest element. - */ - def apply(index: UInt): UInt = { - requireIsHardware(index, "index must be hardware") - - if (length < 1) { - throw new IndexOutOfBoundsException("Collection is empty") - } - - MuxLookup(index, elts.head.asUInt, elts.zipWithIndex.map { case (el, el_index) => el_index.U -> el.asUInt }) - } - /** Strong bulk connect, assigning elements in this MixedVec from elements in a Seq. * * @note the lengths of this and that must match |
