diff options
| author | Martin Schoeberl | 2019-01-25 23:24:01 -0800 |
|---|---|---|
| committer | Richard Lin | 2019-01-25 23:24:01 -0800 |
| commit | 5509cdd4c8332c53151e10ba5bdbe0684af1c05b (patch) | |
| tree | 15f4a7e8f83e0d249918bbce4198160fb2c5360f /src/main/scala/chisel3/util | |
| parent | 4f5ec211cb59f9da37dbe91d0dfcb93c4d3d84c9 (diff) | |
WireDefault instead of WireInit, keep WireInit around (#986)
Diffstat (limited to 'src/main/scala/chisel3/util')
| -rw-r--r-- | src/main/scala/chisel3/util/Arbiter.scala | 4 | ||||
| -rw-r--r-- | src/main/scala/chisel3/util/Decoupled.scala | 4 | ||||
| -rw-r--r-- | src/main/scala/chisel3/util/Enum.scala | 2 |
3 files changed, 5 insertions, 5 deletions
diff --git a/src/main/scala/chisel3/util/Arbiter.scala b/src/main/scala/chisel3/util/Arbiter.scala index 0da4bbc5..0a214581 100644 --- a/src/main/scala/chisel3/util/Arbiter.scala +++ b/src/main/scala/chisel3/util/Arbiter.scala @@ -72,7 +72,7 @@ class LockingRRArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[ (0 until n).map(i => ctrl(i) && grantMask(i) || ctrl(i + n)) } - override protected lazy val choice = WireInit((n-1).asUInt) + override protected lazy val choice = WireDefault((n-1).asUInt) for (i <- n-2 to 0 by -1) when (io.in(i).valid) { choice := i.asUInt } for (i <- n-1 to 1 by -1) @@ -83,7 +83,7 @@ class LockingArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T extends LockingArbiterLike[T](gen, n, count, needsLock) { protected def grant: Seq[Bool] = ArbiterCtrl(io.in.map(_.valid)) - override protected lazy val choice = WireInit((n-1).asUInt) + override protected lazy val choice = WireDefault((n-1).asUInt) for (i <- n-2 to 0 by -1) when (io.in(i).valid) { choice := i.asUInt } } diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala index c3c0d224..105b4528 100644 --- a/src/main/scala/chisel3/util/Decoupled.scala +++ b/src/main/scala/chisel3/util/Decoupled.scala @@ -220,8 +220,8 @@ class Queue[T <: Data](gen: T, private val ptr_match = enq_ptr.value === deq_ptr.value private val empty = ptr_match && !maybe_full private val full = ptr_match && maybe_full - private val do_enq = WireInit(io.enq.fire()) - private val do_deq = WireInit(io.deq.fire()) + private val do_enq = WireDefault(io.enq.fire()) + private val do_deq = WireDefault(io.deq.fire()) when (do_enq) { ram(enq_ptr.value) := io.enq.bits diff --git a/src/main/scala/chisel3/util/Enum.scala b/src/main/scala/chisel3/util/Enum.scala index 92de56ea..eaec3c04 100644 --- a/src/main/scala/chisel3/util/Enum.scala +++ b/src/main/scala/chisel3/util/Enum.scala @@ -15,7 +15,7 @@ import chisel3.internal.chiselRuntimeDeprecated * * @example {{{ * val state_on :: state_off :: Nil = Enum(2) - * val current_state = WireInit(state_off) + * val current_state = WireDefault(state_off) * switch (current_state) { * is (state_on) { * ... |