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| author | Richard Lin | 2019-01-21 16:24:43 -0800 |
|---|---|---|
| committer | GitHub | 2019-01-21 16:24:43 -0800 |
| commit | 9e992816e570284193e121cd9c24503fd8cb4427 (patch) | |
| tree | 90205ab0c936d50f4853bb7dc6293a4b62d47edf /src/main/scala/chisel3/util | |
| parent | 3b3405e8bd496749dcb47e17156c0224a6f8a496 (diff) | |
Unify internal (chisel3.core) and external (chisel3 / chisel3.experimental) Module class names (#994)
Diffstat (limited to 'src/main/scala/chisel3/util')
| -rw-r--r-- | src/main/scala/chisel3/util/Decoupled.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala index d2a6552d..c3c0d224 100644 --- a/src/main/scala/chisel3/util/Decoupled.scala +++ b/src/main/scala/chisel3/util/Decoupled.scala @@ -21,7 +21,7 @@ abstract class ReadyValidIO[+T <: Data](gen: T) extends Bundle { // Compatibility hack for rocket-chip private val genType = (DataMirror.internal.isSynthesizable(gen), chisel3.internal.Builder.currentModule) match { - case (true, Some(module: chisel3.core.ImplicitModule)) + case (true, Some(module: chisel3.core.MultiIOModule)) if !module.compileOptions.declaredTypeMustBeUnbound => chiselTypeOf(gen) case _ => gen } |