From 9e992816e570284193e121cd9c24503fd8cb4427 Mon Sep 17 00:00:00 2001
From: Richard Lin
Date: Mon, 21 Jan 2019 16:24:43 -0800
Subject: Unify internal (chisel3.core) and external (chisel3 /
 chisel3.experimental) Module class names (#994)

---
 src/main/scala/chisel3/util/Decoupled.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/main/scala/chisel3/util')

diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index d2a6552d..c3c0d224 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -21,7 +21,7 @@ abstract class ReadyValidIO[+T <: Data](gen: T) extends Bundle
 {
   // Compatibility hack for rocket-chip
   private val genType = (DataMirror.internal.isSynthesizable(gen), chisel3.internal.Builder.currentModule) match {
-    case (true, Some(module: chisel3.core.ImplicitModule))
+    case (true, Some(module: chisel3.core.MultiIOModule))
         if !module.compileOptions.declaredTypeMustBeUnbound => chiselTypeOf(gen)
     case _ => gen
   }
-- 
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