Unify internal (chisel3.core) and external (chisel3 / chisel3.experimental) Module class names (#994)

3 files changed, 4 insertions, 4 deletions

diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
index ac4bf8e7..68513423 100644
--- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala
+++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
@@ -110,7 +110,7 @@ private class Emitter(circuit: Circuit) {
     */
   private def moduleDecl(m: Component): String = m.id match {
     case _: chisel3.core.BaseBlackBox => newline + s"extmodule ${m.name} : "
-    case _: chisel3.core.UserModule => newline + s"module ${m.name} : "
+    case _: chisel3.core.RawModule => newline + s"module ${m.name} : "
   }
 
   /** Generates the FIRRTL module definition.
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index e79a1186..3b1275f6 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -430,8 +430,8 @@ package object chisel3 {    // scalastyle:ignore package.object.name
     val dontTouch = chisel3.core.dontTouch
 
     type BaseModule = chisel3.core.BaseModule
-    type MultiIOModule = chisel3.core.ImplicitModule
-    type RawModule = chisel3.core.UserModule
+    type RawModule = chisel3.core.RawModule
+    type MultiIOModule = chisel3.core.MultiIOModule
     type ExtModule = chisel3.core.ExtModule
 
     val IO = chisel3.core.IO
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index d2a6552d..c3c0d224 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -21,7 +21,7 @@ abstract class ReadyValidIO[+T <: Data](gen: T) extends Bundle
 {
   // Compatibility hack for rocket-chip
   private val genType = (DataMirror.internal.isSynthesizable(gen), chisel3.internal.Builder.currentModule) match {
-    case (true, Some(module: chisel3.core.ImplicitModule))
+    case (true, Some(module: chisel3.core.MultiIOModule))
         if !module.compileOptions.declaredTypeMustBeUnbound => chiselTypeOf(gen)
     case _ => gen
   }