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* RawModule with no reset should be able to use withClock method.
- refactor ClockAndReset
- now has `clockOpt: Option[Clock]` and `resetOpt: Option[Reset]` constructor params
- convenience methods clock and reset tries to deref the option
- ClockAndReset.empty is factory method for (None, None)
- In Builder
- forcedClock does not check resetOpt now
- forcedReset does not check clockOpt now
- withClock no longer looks at resetOpt
- withReset no longer looks at clockOpt
- Module starts with empty ClockAndReset
* RawModule with no reset should be able to use withClock method.
Refactor again based on @ducky64 comments
- refactor away ClockAndReset, now builder just has a
- currentClock
- currentReset
- withClock, withRest, withClockAndReset just use these fields directly
* RawModule with no reset should be able to use withClock method.
- Fixed typo in withReset handler, now picks up new reset
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This removes uses of @usecase. This is deprecated in Scala 2.13.x.
Additionally, scala generious spurious warnings if you use @usecase in
a non-abstract class. (It thinks that this is an abstract member of
something concrete.)
The guidance from upstream Scala is to be explicit about how to use
your API via @example.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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* IO(Analog) fixed for RawModule
* Add a Analog Port for RawModule test & spec
* Fixes around Module instantiation and ports in AnalogPortRawModuleTest
* Shorten Comment
* Add Data.isSynthesizable to distinguish SampleElementBinding
This helps clarify the notion of being bound but not hardware.
Data.topBindingOpt is now used to get the *actual* top binding,
including across SampleElements (eg. in Analog checking that the top is
bound to a Port or a Wire)
* Fix pretty printing for Vec
* Refactor tests for Vec of Analog, add test for Vec of Bundle of Analog
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Closes #1075.
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This is necessary to support code that imports an implicit conversion
from Int to UInt
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Create Chisel IR Port() in a way that Converter is happy with.
Also add more extensive test suite for future-proofing.
Close #1063
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- Introduce internal helper `castToInt`, which issues an error when the input
BigInt can't be represented as Int.
- Use `castToInt` wherever we were using `toInt` in a potentially unsafe way.
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This is necessary to use ChiselEnum in aggregates where things are
casted using .asTypeOf
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Previously, including an empty aggregate in a Bundle would cause
a MixedDirectionAggregateException because it has no elements and thus
doesn't have a direction
* Add SampleElementBinding for Vec sample elements
* Add ActualDirection.Empty for bound empty aggregates
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Force clients to access 'DontCare' through the chisel3 package to ensure it's created as a chisel3 object and not a client object.
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* Turned off strong enum annotations because they weren't working with Vec
indexes
* Add new EnumVecAnnotation for vecs of enums and vecs of bundles with
enum fields
* Changed Clock's width parameter back to a fixed constant value of 1
* Fixed enum annotations for Vecs of Bundles which contain enum elements
* Fixed usage of "when/otherwise" to use consistent style
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* Update style warnings now that subprojects are aggregated.
Use "scalastyle-test-config.xml" for scalastyle config in tests.
Enable "_" in method names and accept method names ending in "_=".
Re-sync scalastyle-test-config.xml with scalastyle-config.xml
* Remove bogus tests that crept in with git add
* Add missing import.
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Compatibility for rename introduced by #994
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toString on Data subtypes will now print the type and optionally binding information including literals and IO names as feasible.
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Module class names (#994)
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It performs the operation (x === 0.U), just like in C. The scaladoc
incorrectly described it as performing the operation !x(0). (Obviously, these
are equivalent for Bool, but not for UInt in general).
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In the case that the width is known, we can emit one fewer Firrtl node.
This obviously synthesizes the same way, but compiles/simulates faster.
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* Fix width propagation of non-literals in WireInit and RegInit
* Change .getWidth to throw an exception instead of calling .get
* Add utilities for checking inferred vs. known widths
* Add tests for Wire, WireInit, Reg, and RegInit width inference
* Add ScalaDoc for Reg, Wire, RegInit, and WireInit
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This is semantically equivalent, but gets rid of a bunch of Firrtl text.
It also gets rid of a bunch of Verilog, because Firrtl is capable of
pattern-matching the new expression into SubWrap. The effect is that
we now get
wire [4:0] in;
wire [4:0] res;
assign res = 5'h0 - in;
instead of
wire [4:0] in;
wire [5:0] _T_40;
wire [5:0] _T_41;
wire [4:0] res;
assign _T_40 = 5'h0 - in;
assign _T_41 = $unsigned(_T_40);
assign res = _T_41[4:0];
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The expanded version substituted in by the macro was misspelled, renamed
from toBools -> do_toBools as expected by the macro
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- Trim stack trace to show better, reduced information to the user
- Add --full-stacktrace to FIRRTL option to show full stack trace
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Fixes #893
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* Turned off strong enum annotations because they weren't working
with Vec indexes
* Ignore annotation tests using ScalaTest's 'ignore', rather than
by commenting them out
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This wraps the evaluation of BaseModule.name in try/catch to look for a
NullPointerException that may result from trying to evaluate desiredName
before it's ready. This catches a test case of using a desiredName that
depends on a later defined eager subinstance.
h/t @jackkoenig
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This changes BaseModule.name to be lazy (instead of eager) to enable a
desiredName to be a function of a sub-instance. This includes a test case
showing the new behavior.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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