Fix miscellaneous Scaladoc warnings

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

3 files changed, 9 insertions, 10 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Annotation.scala b/chiselFrontend/src/main/scala/chisel3/core/Annotation.scala
index b2c9ea78..b7e82f63 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Annotation.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Annotation.scala
@@ -5,7 +5,6 @@ package chisel3.core
 import scala.language.existentials
 
 import chisel3.internal.{Builder, InstanceId}
-import chisel3.core.ImplicitModule
 import firrtl.Transform
 import firrtl.annotations.{Annotation, CircuitName, ComponentName, ModuleName}
 import firrtl.transforms.{DontTouchAnnotation, NoDedupAnnotation}
@@ -30,9 +29,10 @@ object ChiselAnnotation {
     }
 }
 
-/** Mixin for [[ChiselAnnotation]] that instantiates an associated FIRRTL Transform when this
-  * Annotation is present during a run of [[chisel3.Driver.execute]]. Automatic Transform
-  * instantiation is *not* supported when the Circuit and Annotations are serialized before invoking
+/** Mixin for [[ChiselAnnotation]] that instantiates an associated FIRRTL Transform when this Annotation is present
+  * during a run of
+  * [[Driver$.execute(args:Array[String],dut:()=>chisel3\.experimental\.RawModule)* Driver.execute]].
+  * Automatic Transform instantiation is *not* supported when the Circuit and Annotations are serialized before invoking
   * FIRRTL.
   */
 // TODO There should be a FIRRTL API for this instead
@@ -99,7 +99,7 @@ object dontTouch { // scalastyle:ignore object.name
   *        val b = Input(UInt(32.W))
   *        val out = Output(UInt(32.W))
   *      })
-  *      override def desiredName = s"adder_$myNname"
+  *      override def desiredName = "adder_" + myNname
   *      io.out := io.a + io.b
   *    })
   *    doNotDedup(m)
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index 424db5cb..b18b27e5 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -1285,7 +1285,7 @@ sealed class Bool() extends UInt(1.W) with Reset {
     *
     * @param that a hardware $coll
     * @return the lgocial or of this $coll and `that`
-    * @note this is equivalent to [[Bool.|]]
+    * @note this is equivalent to [[Bool!.|(that:chisel3\.core\.Bool)* Bool.|)]]
     * @group Logical
     */
   def || (that: Bool): Bool = macro SourceInfoTransform.thatArg
@@ -1297,7 +1297,7 @@ sealed class Bool() extends UInt(1.W) with Reset {
     *
     * @param that a hardware $coll
     * @return the lgocial and of this $coll and `that`
-    * @note this is equivalent to [[Bool.&]]
+    * @note this is equivalent to [[Bool!.&(that:chisel3\.core\.Bool)* Bool.&]]
     * @group Logical
     */
   def && (that: Bool): Bool = macro SourceInfoTransform.thatArg
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
index 51ad154f..3ce79786 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
@@ -498,7 +498,7 @@ abstract class Data extends HasId with NamedComponent with SourceInfoDoc { // sc
     case Some(BundleLitBinding(litMap)) => None  // this API does not support Bundle literals
     case _ => None
   }
- 
+
   def isLit(): Boolean = litArg.isDefined
 
   /**
@@ -680,7 +680,7 @@ object WireDefault {
     x
   }
 
-  /** Construct a [[Wire]] with a type template and a [[DontCare]] default
+  /** Construct a [[Wire]] with a type template and a [[chisel3.DontCare]] default
     * @param t The type template used to construct this [[Wire]]
     * @param init The default connection to this [[Wire]], can only be [[DontCare]]
     * @note This is really just a specialized form of `apply[T <: Data](t: T, init: T): T` with [[DontCare]] as `init`
@@ -740,4 +740,3 @@ private[chisel3] object DontCare extends Element {
   // DontCare's only match themselves.
   private[core] def typeEquivalent(that: chisel3.core.Data): Boolean = that == DontCare
 }
-