Fix miscellaneous Scaladoc warnings

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

8 files changed, 25 insertions, 30 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Annotation.scala b/chiselFrontend/src/main/scala/chisel3/core/Annotation.scala
index b2c9ea78..b7e82f63 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Annotation.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Annotation.scala
@@ -5,7 +5,6 @@ package chisel3.core
 import scala.language.existentials
 
 import chisel3.internal.{Builder, InstanceId}
-import chisel3.core.ImplicitModule
 import firrtl.Transform
 import firrtl.annotations.{Annotation, CircuitName, ComponentName, ModuleName}
 import firrtl.transforms.{DontTouchAnnotation, NoDedupAnnotation}
@@ -30,9 +29,10 @@ object ChiselAnnotation {
     }
 }
 
-/** Mixin for [[ChiselAnnotation]] that instantiates an associated FIRRTL Transform when this
-  * Annotation is present during a run of [[chisel3.Driver.execute]]. Automatic Transform
-  * instantiation is *not* supported when the Circuit and Annotations are serialized before invoking
+/** Mixin for [[ChiselAnnotation]] that instantiates an associated FIRRTL Transform when this Annotation is present
+  * during a run of
+  * [[Driver$.execute(args:Array[String],dut:()=>chisel3\.experimental\.RawModule)* Driver.execute]].
+  * Automatic Transform instantiation is *not* supported when the Circuit and Annotations are serialized before invoking
   * FIRRTL.
   */
 // TODO There should be a FIRRTL API for this instead
@@ -99,7 +99,7 @@ object dontTouch { // scalastyle:ignore object.name
   *        val b = Input(UInt(32.W))
   *        val out = Output(UInt(32.W))
   *      })
-  *      override def desiredName = s"adder_$myNname"
+  *      override def desiredName = "adder_" + myNname
   *      io.out := io.a + io.b
   *    })
   *    doNotDedup(m)
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index 424db5cb..b18b27e5 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -1285,7 +1285,7 @@ sealed class Bool() extends UInt(1.W) with Reset {
     *
     * @param that a hardware $coll
     * @return the lgocial or of this $coll and `that`
-    * @note this is equivalent to [[Bool.|]]
+    * @note this is equivalent to [[Bool!.|(that:chisel3\.core\.Bool)* Bool.|)]]
     * @group Logical
     */
   def || (that: Bool): Bool = macro SourceInfoTransform.thatArg
@@ -1297,7 +1297,7 @@ sealed class Bool() extends UInt(1.W) with Reset {
     *
     * @param that a hardware $coll
     * @return the lgocial and of this $coll and `that`
-    * @note this is equivalent to [[Bool.&]]
+    * @note this is equivalent to [[Bool!.&(that:chisel3\.core\.Bool)* Bool.&]]
     * @group Logical
     */
   def && (that: Bool): Bool = macro SourceInfoTransform.thatArg
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
index 51ad154f..3ce79786 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
@@ -498,7 +498,7 @@ abstract class Data extends HasId with NamedComponent with SourceInfoDoc { // sc
     case Some(BundleLitBinding(litMap)) => None  // this API does not support Bundle literals
     case _ => None
   }
- 
+
   def isLit(): Boolean = litArg.isDefined
 
   /**
@@ -680,7 +680,7 @@ object WireDefault {
     x
   }
 
-  /** Construct a [[Wire]] with a type template and a [[DontCare]] default
+  /** Construct a [[Wire]] with a type template and a [[chisel3.DontCare]] default
     * @param t The type template used to construct this [[Wire]]
     * @param init The default connection to this [[Wire]], can only be [[DontCare]]
     * @note This is really just a specialized form of `apply[T <: Data](t: T, init: T): T` with [[DontCare]] as `init`
@@ -740,4 +740,3 @@ private[chisel3] object DontCare extends Element {
   // DontCare's only match themselves.
   private[core] def typeEquivalent(that: chisel3.core.Data): Boolean = that == DontCare
 }
-
diff --git a/coreMacros/src/main/scala/chisel3/SourceInfoDoc.scala b/coreMacros/src/main/scala/chisel3/SourceInfoDoc.scala
index 4e7533d4..4b6b0a8c 100644
--- a/coreMacros/src/main/scala/chisel3/SourceInfoDoc.scala
+++ b/coreMacros/src/main/scala/chisel3/SourceInfoDoc.scala
@@ -15,27 +15,23 @@ package chisel3
   *   <br>
   *
   *   The equivalent public-facing methods do not have the `do_` prefix or have the same name. Use and look at the
-  *   documentation for those. If you want left shift, use `<<`, not `do_<<`. If you want comversion to a [[Seq]] of
-  *   [[Bool]]s look at the `asBools` above, not the one below. Users can safely ignore every method in this group!
-  *   <br>
-  *   <br>
+  *   documentation for those. If you want left shift, use `<<`, not `do_<<`. If you want conversion to a
+  *   [[scala.collection.Seq Seq]] of [[Bool]]s look at the `asBools` above, not the one below. Users can safely ignore
+  *   every method in this group! <br> <br>
   *
   *   🐉🐉🐉 '''Here be dragons...''' 🐉🐉🐉
   *   <br>
   *   <br>
   *
-  *   These `do_X` methods are used to enable both implicit passing of [[SourceInfo]] and
-  *   [[chisel3.core.CompileOptions]] while also supporting chained apply methods. In effect all "normal" methods that
-  *   you, as a user, will use in your designs, are converted to their "hidden", `do_*`, via macro transformations.
-  *   Without using macros here, only one of the above wanted behaviors is allowed (implicit passing and chained
-  *   applies)---the compiler interprets a chained apply as an explicit 'implicit' argument and will throw type errors.
-  *   <br>
-  *   <br>
+  *   These `do_X` methods are used to enable both implicit passing of SourceInfo and [[chisel3.core.CompileOptions]]
+  *   while also supporting chained apply methods. In effect all "normal" methods that you, as a user, will use in your
+  *   designs, are converted to their "hidden", `do_*`, via macro transformations. Without using macros here, only one
+  *   of the above wanted behaviors is allowed (implicit passing and chained applies)---the compiler interprets a
+  *   chained apply as an explicit 'implicit' argument and will throw type errors. <br> <br>
   *
-  *   The "normal", public-facing methods then take no [[SourceInfo]]. However, a macro transforms this public-facing
-  *   method into a call to an internal, hidden `do_*` that takes an explicit [[SourceInfo]] by inserting an
-  *   `implicitly[SourceInfo]` as the explicit argument.
-  * </p>
+  *   The "normal", public-facing methods then take no SourceInfo. However, a macro transforms this public-facing method
+  *   into a call to an internal, hidden `do_*` that takes an explicit SourceInfo by inserting an
+  *   `implicitly[SourceInfo]` as the explicit argument. </p>
   *
   * @groupprio SourceInfoTransformMacro 1001
   */
diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala
index d0f6f6bd..9071491b 100644
--- a/src/main/scala/chisel3/Driver.scala
+++ b/src/main/scala/chisel3/Driver.scala
@@ -151,7 +151,7 @@ object Driver extends BackendCompilationUtilities {
     * Emit the annotations of a circuit
     *
     * @param ir The circuit containing annotations to be emitted
-    * @param optName An optional filename (will use s"${ir.name}.json" otherwise)
+    * @param optName An optional filename (will use s"\${ir.name}.json" otherwise)
     */
   def dumpAnnotations(ir: Circuit, optName: Option[File]): File = {
     val f = optName.getOrElse(new File(ir.name + ".anno.json"))
diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala
index 4ba762b5..c6458b9d 100644
--- a/src/main/scala/chisel3/util/Valid.scala
+++ b/src/main/scala/chisel3/util/Valid.scala
@@ -61,7 +61,7 @@ class Valid[+T <: Data](gen: T) extends Bundle {
   * }}}
   *
   * In addition to adding the `valid` bit, a [[Valid.fire]] method is also added that returns the `valid` bit. This
-  * provides a similarly named interface to [[DecoupledIO.fire]].
+  * provides a similarly named interface to [[DecoupledIO]]'s fire.
   *
   * @see [[Decoupled$ DecoupledIO Factory]]
   * @see [[Irrevocable$ IrrevocableIO Factory]]
diff --git a/src/main/scala/chisel3/util/experimental/BoringUtils.scala b/src/main/scala/chisel3/util/experimental/BoringUtils.scala
index 67a6b6d0..a6f2d52a 100644
--- a/src/main/scala/chisel3/util/experimental/BoringUtils.scala
+++ b/src/main/scala/chisel3/util/experimental/BoringUtils.scala
@@ -18,7 +18,7 @@ import chisel3.internal.Namespace
 class BoringUtilsException(message: String) extends Exception(message)
 
 /** Utilities for generating synthesizable cross module references that "bore" through the hierarchy. The underlying
-  * cross module connects are handled by FIRRTL's Wiring Transform ([[firrtl.passes.wiring.WiringTransform]]).
+  * cross module connects are handled by FIRRTL's Wiring Transform.
   *
   * Consider the following exmple where you want to connect a component in one module to a component in another. Module
   * `Constant` has a wire tied to `42` and `Expect` will assert unless connected to `42`:
diff --git a/src/main/scala/chisel3/util/experimental/Inline.scala b/src/main/scala/chisel3/util/experimental/Inline.scala
index 8ec5219b..753c36af 100644
--- a/src/main/scala/chisel3/util/experimental/Inline.scala
+++ b/src/main/scala/chisel3/util/experimental/Inline.scala
@@ -28,8 +28,8 @@ import firrtl.annotations.{CircuitName, ModuleName, ComponentName, Annotation}
   * class Bar extends Module with Internals with HasSub
   * /* The resulting instances will be:
   *  - Top
-  *  - Top.x$sub
-  *  - Top.y$sub
+  *  - Top.x\$sub
+  *  - Top.y\$sub
   *  - Top.z
   *  - Top.z.sub */
   * class Top extends Module with Internals {