diff options
| author | Richard Lin | 2019-01-21 21:31:06 -0800 |
|---|---|---|
| committer | GitHub | 2019-01-21 21:31:06 -0800 |
| commit | 99bb15f13491637f1c7ce58edb5ba494efc810dc (patch) | |
| tree | b257572551776759c29876fff68aa9f079498eb1 /chiselFrontend | |
| parent | 9e992816e570284193e121cd9c24503fd8cb4427 (diff) | |
Support DontCare in Mux and cloneSupertype (#995)
Diffstat (limited to 'chiselFrontend')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Data.scala | 19 | ||||
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Mux.scala | 16 |
2 files changed, 26 insertions, 9 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala index e56412e6..cf6dabdd 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala @@ -113,8 +113,11 @@ private[core] object cloneSupertype { compileOptions: CompileOptions): T = { require(!elts.isEmpty, s"can't create $createdType with no inputs") - if (elts.head.isInstanceOf[Bits]) { - val model: T = elts reduce { (elt1: T, elt2: T) => ((elt1, elt2) match { + val filteredElts = elts.filter(_ != DontCare) + require(!filteredElts.isEmpty, s"can't create $createdType with only DontCare inputs") + + if (filteredElts.head.isInstanceOf[Bits]) { + val model: T = filteredElts reduce { (elt1: T, elt2: T) => ((elt1, elt2) match { case (elt1: Bool, elt2: Bool) => elt1 case (elt1: Bool, elt2: UInt) => elt2 // TODO: what happens with zero width UInts? case (elt1: UInt, elt2: Bool) => elt1 // TODO: what happens with zero width UInts? @@ -140,13 +143,13 @@ private[core] object cloneSupertype { model.cloneTypeFull } else { - for (elt <- elts.tail) { - require(elt.getClass == elts.head.getClass, - s"can't create $createdType with heterogeneous types ${elts.head.getClass} and ${elt.getClass}") - require(elt typeEquivalent elts.head, - s"can't create $createdType with non-equivalent types ${elts.head} and ${elt}") + for (elt <- filteredElts.tail) { + require(elt.getClass == filteredElts.head.getClass, + s"can't create $createdType with heterogeneous types ${filteredElts.head.getClass} and ${elt.getClass}") + require(elt typeEquivalent filteredElts.head, + s"can't create $createdType with non-equivalent types ${filteredElts.head} and ${elt}") } - elts.head.cloneTypeFull + filteredElts.head.cloneTypeFull } } } diff --git a/chiselFrontend/src/main/scala/chisel3/core/Mux.scala b/chiselFrontend/src/main/scala/chisel3/core/Mux.scala index 56c145b5..7dd1b98b 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Mux.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Mux.scala @@ -32,6 +32,20 @@ object Mux extends SourceInfoDoc { requireIsHardware(con, "mux true value") requireIsHardware(alt, "mux false value") val d = cloneSupertype(Seq(con, alt), "Mux") - pushOp(DefPrim(sourceInfo, d, MultiplexOp, cond.ref, con.ref, alt.ref)) + val conRef = con match { // this matches chisel semantics (DontCare as object) to firrtl semantics (invalidate) + case DontCare => + val dcWire = Wire(d) + dcWire := DontCare + dcWire.ref + case _ => con.ref + } + val altRef = alt match { + case DontCare => + val dcWire = Wire(d) + dcWire := DontCare + dcWire.ref + case _ => alt.ref + } + pushOp(DefPrim(sourceInfo, d, MultiplexOp, cond.ref, conRef, altRef)) } } |
