diff options
| author | Paul Rigge | 2019-05-01 19:55:21 -0700 |
|---|---|---|
| committer | edwardcwang | 2019-05-01 19:55:20 -0700 |
| commit | 94d5b90493b42dd2c85d0d94ea707a69160d0536 (patch) | |
| tree | 39c3fc0b6e05f5b05c5d826203c2e04092217fcd /chiselFrontend | |
| parent | c1ab9e7afd5072c11d879db913e1b553c7fe0dbe (diff) | |
Make asTypeOf work for bundles with zero-width fields. (#1079)
Closes #1075.
Diffstat (limited to 'chiselFrontend')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala index 35f53013..c75974f0 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala @@ -66,8 +66,16 @@ sealed abstract class Aggregate extends Data { var i = 0 val bits = WireDefault(UInt(this.width), that) // handles width padding for (x <- flatten) { - x.connectFromBits(bits(i + x.getWidth - 1, i)) - i += x.getWidth + val fieldWidth = x.getWidth + if (fieldWidth > 0) { + x.connectFromBits(bits(i + fieldWidth - 1, i)) + i += fieldWidth + } else { + // There's a zero-width field in this bundle. + // Zero-width fields can't really be assigned to, but the frontend complains if there are uninitialized fields, + // so we assign it to DontCare. We can't use connectFromBits() on DontCare, so use := instead. + x := DontCare + } } } } |
