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chiselX
abstract-module
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scala3-main-test
scala3-support
scala3-support-chisel6
Chisel with SFC compatibility
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chiselFrontend
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Author
2016-07-20
More literal/width rangling.
Jim Lawson
2016-07-20
Distinguish between ?Int.Lit and ?Int.width
Jim Lawson
2016-07-20
Compile ok.
Jim Lawson
2016-07-19
Fixes for only connectwrap version.
Jim Lawson
2016-07-19
Merge in "complete" versions of Mem, Reg.
Jim Lawson
2016-07-19
Fix LitBinding and MultiAssign tests.
Jim Lawson
2016-07-19
Remove explicit literal binding.
Jim Lawson
2016-07-19
Incorporate connection logic.
Jim Lawson
2016-07-19
Merge branch 'sdtwigg_rebase_renamechisel3' into sdtwigg_wrap_renamechisel3
Jim Lawson
2016-07-18
Update Chisel -> chisel3 references.
Jim Lawson
2016-07-18
Rename "Chisel" to "chisel3" (only git mv).
Jim Lawson
2016-06-21
Most of the remaining tests with Module, IO wrapping.
Jim Lawson
2016-06-21
New Module, IO, Input/Output wrapping.
Jim Lawson
2016-06-08
For Module instances we haven't named, suggest the Module class name
Andrew Waterman
2016-06-01
Fix a fairly serious bug whereby Vec's could incorrectly compare as equal (#204)
Wesley W. Terpstra
2016-05-31
Move BitPat out of core/frontend, add implicit conversion
Ducky
2016-05-26
Fix type constraint on PriorityMux
Andrew Waterman
2016-05-20
Merge pull request #186 from ucb-bar/sloc_impl
Richard Lin
2016-05-20
Implementation of source locators
ducky
2016-05-10
Some -> Option
Donggyu Kim
2016-05-10
Move emit out of IR
ducky
2016-05-10
Have Bits.toBools return Seq, not Vec
Andrew Waterman
2016-05-10
Relax Mem write-masks to Seq, rather than Vec
Andrew Waterman
2016-05-09
fix width inference in enum
Donggyu Kim
2016-05-09
get -> getOrElse
Donggyu Kim
2016-05-05
Move Chisel API into separate chiselFrontend compilation unit in preparation ...
ducky