More literal/width rangling.

3 files changed, 2 insertions, 6 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index 3580b5f3..ee0acd86 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -518,8 +518,6 @@ sealed class UInt private[core] (width: Width, lit: Option[ULit] = None)
 private[core] sealed trait UIntFactory {
   /** Create a UInt type with inferred width. */
   def apply(): UInt = apply(Width())
-  /** Create a UInt type or port with fixed width. */
-  def apply(width: Int): UInt = apply(Width(width))
   /** Create a UInt port with specified width. */
   def apply(width: Width): UInt = new UInt(width)
   /** Create a UInt with a specified width - compatibility with Chisel2. */
@@ -677,8 +675,6 @@ object SInt {
   /** Create an SInt type with inferred width. */
   def apply(): SInt = apply(Width())
   /** Create a SInt type or port with fixed width. */
-  def apply(width: Int): SInt = apply(Width(width))
-  /** Create an SInt type with specified width. */
   def apply(width: Width): SInt = new SInt(width)
   /** Create a SInt type or port with fixed width. */
   def width(width: Int): SInt = apply(Width(width))
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Reg.scala b/chiselFrontend/src/main/scala/chisel3/core/Reg.scala
index b46b96ef..e0607520 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Reg.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Reg.scala
@@ -11,7 +11,7 @@ object Reg {
   private[core] def makeType[T <: Data](t: T = null, next: T = null,
 init: T = null): T = {
     if (t ne null) {
-      Binding.checkUnbound(t, s"t ($t) must be unbound Type. Try using newType?")
+      Binding.checkUnbound(t, s"t ($t) must be unbound Type. Try using cloneType?")
       t.cloneType
     } else if (next ne null) {
       next.cloneTypeWidth(Width())
diff --git a/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala b/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala
index c1ec6b90..b06fd7a5 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala
@@ -51,7 +51,7 @@ private[chisel3] object SeqUtils {
     if (in.tail.isEmpty) {
       in.head._2
     } else {
-      val masked = for ((s, i) <- in) yield Mux(s, i.toBits, Bits(0))
+      val masked = for ((s, i) <- in) yield Mux(s, i.toBits, Bits.Lit(0))
       val width = in.map(_._2.width).reduce(_ max _)
       in.head._2.cloneTypeWidth(width).fromBits(masked.reduceLeft(_|_))
     }