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authorducky2016-05-10 14:58:14 -0700
committerducky2016-05-10 15:06:13 -0700
commitce6ad2116284291df24b5c8a2536deaad0ec7f04 (patch)
tree12a446cb4dc3be66dff75385b471b425e109e773 /chiselFrontend
parentaf6173d011ec19d80e0ffce0ff9a5658f876225e (diff)
Move emit out of IR
Diffstat (limited to 'chiselFrontend')
-rw-r--r--chiselFrontend/src/main/scala/Chisel/internal/firrtl/Emitter.scala4
-rw-r--r--chiselFrontend/src/main/scala/Chisel/internal/firrtl/IR.scala4
2 files changed, 5 insertions, 3 deletions
diff --git a/chiselFrontend/src/main/scala/Chisel/internal/firrtl/Emitter.scala b/chiselFrontend/src/main/scala/Chisel/internal/firrtl/Emitter.scala
index b690d974..34547503 100644
--- a/chiselFrontend/src/main/scala/Chisel/internal/firrtl/Emitter.scala
+++ b/chiselFrontend/src/main/scala/Chisel/internal/firrtl/Emitter.scala
@@ -3,6 +3,10 @@
package Chisel.internal.firrtl
import Chisel._
+private[Chisel] object Emitter {
+ def emit(circuit: Circuit): String = new Emitter(circuit).toString
+}
+
private class Emitter(circuit: Circuit) {
override def toString: String = res.toString
diff --git a/chiselFrontend/src/main/scala/Chisel/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/Chisel/internal/firrtl/IR.scala
index 1e06a663..91dcf5d2 100644
--- a/chiselFrontend/src/main/scala/Chisel/internal/firrtl/IR.scala
+++ b/chiselFrontend/src/main/scala/Chisel/internal/firrtl/IR.scala
@@ -182,6 +182,4 @@ case class Printf(clk: Arg, formatIn: String, ids: Seq[Arg]) extends Command {
}
}
-case class Circuit(name: String, components: Seq[Component]) {
- def emit: String = new Emitter(this).toString
-}
+case class Circuit(name: String, components: Seq[Component])