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authorJim Lawson2016-07-19 16:16:35 -0700
committerJim Lawson2016-07-19 16:16:35 -0700
commit21a3c12b309df88cdb8114c01ef35b044282d647 (patch)
treea7b6996dd584d1cd186caedd63d63a09559a318c /chiselFrontend
parente27079d2957c689affce66f15e9d1bf29418ad34 (diff)
Fix LitBinding and MultiAssign tests.
Diffstat (limited to 'chiselFrontend')
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Bits.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index df1296dd..1bdf66f1 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -530,7 +530,7 @@ private[core] sealed trait UIntFactory {
val lit = ULit(value, width)
val result = new UInt(lit.width, Some(lit))
// Bind result to being an Literal
-// result.binding = LitBinding()
+ result.binding = LitBinding()
result
}