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path: root/chiselFrontend/src/main
AgeCommit message (Expand)Author
2018-09-07Add Bool ScalaDoc documentationSchuyler Eldridge
2018-09-07Add SInt ScalaDoc documentationSchuyler Eldridge
2018-09-07Add UInt ScalaDoc documentationSchuyler Eldridge
2018-09-07Add Num ScalaDoc documentationSchuyler Eldridge
2018-09-07Add Bits ScalaDoc documentationSchuyler Eldridge
2018-09-07Put := and <> methods in Connect ScalaDoc groupSchuyler Eldridge
2018-09-07Put do_* methods in SourceInfoTransformMacro groupSchuyler Eldridge
2018-09-07Add Logical ScalaDoc group to NumSchuyler Eldridge
2018-09-07Add Comparison ScalaDoc group to NumSchuyler Eldridge
2018-09-07Add Arithmetic ScalaDoc group to NumSchuyler Eldridge
2018-09-07Add Bitwise ScalaDoc group to BitsSchuyler Eldridge
2018-09-07Add Connect ScalaDoc group to DataSchuyler Eldridge
2018-08-22Update class name in error messageEdward Wang
2018-08-22Use a mix-in to override Seq errorEdward Wang
2018-08-22Warn user that using Seq for hardware construction in Bundle is not supportedEdward Wang
2018-07-31Cleanup implicit conversions (#868)Jack Koenig
2018-07-31Ensure names work for bundles and literals. (#853)Jim Lawson
2018-07-31Revert removal of bit extraction const prop for literals (#857)Jack Koenig
2018-07-10Fix use of read-only refs on rhs of connect in compatibility mode (#854)Jack Koenig
2018-07-04Change wording of internal failureRichard Lin
2018-07-04Fix strict namerRichard Lin
2018-07-04Remove forceName rom BlackBox/ExtModule, filter out forceName in UserModuleRichard Lin
2018-07-04Prefer litValue, eliminate litToBigIntducky
2018-07-04Change [public] Data.elementLitArg => [protected] Aggregate.litArgOfBitsducky
2018-07-04Style fixesducky
2018-07-04binding => topBinding so that partial Bundles work and undefined Bundle membe...ducky
2018-07-04properly fix undefined clock/reset issuesducky
2018-07-04Comment out assertion test, fix ref generationRichard Lin
2018-07-04unbrokenducky
2018-07-04still brokenducky
2018-07-04brokenducky
2018-07-04styleducky
2018-07-04Run-unique idsducky
2018-07-04bundle literal mockup, but broken =(Richard Lin
2018-07-04refactoring of lit and ref implementationsRichard Lin
2018-07-04work on new style literal accessorsducky
2018-07-04Infrastructure for bundle literalsducky
2018-07-02Direct to FIRRTL (#829)Jack Koenig
2018-06-29Catch returns from within when blocks and provide an error message (#842)Jack Koenig
2018-06-20Programmatic Port Creation (#833)Jack Koenig
2018-06-01Literals set their ref so they no longer get named (#826)Jack Koenig
2018-05-31Suggest wrapping in Wire(_) or IO(_) in requireIsHardware (#827)Jack Koenig
2018-05-24Use Vec.apply instead of new Vec in VecInit.apply (#825)Jack Koenig
2018-05-24Remove extraneous traversal in cloneSupertype (#824)Jack Koenig
2018-05-24Fix UIntToOH for output widths larger than 2^(input width) (#823)Andrew Waterman
2018-04-26Minor edits to wordingedwardcwang
2018-04-24Make Mem and SyncReadMem constructors private (#816)Andrew Waterman
2018-04-22Add Module.currentModule for getting a reference to the current Module (#810)Jack Koenig
2018-03-23Fallback null insertion for autoclonetype (#801)Richard Lin
2018-03-06Fix SyncReadMem.read; add test (#796)Andrew Waterman