diff options
| author | Richard Lin | 2018-07-03 18:04:47 -0600 |
|---|---|---|
| committer | Richard Lin | 2018-07-04 18:39:28 -0500 |
| commit | f75366ce5c9d6c676f27aa7980637cb118a520bd (patch) | |
| tree | 7bed722173b8bda6d34871cf31fb1a389c340dce /chiselFrontend/src/main | |
| parent | 46f0aa3a779f433c95fd6d8885572d7a0b827015 (diff) | |
Fix strict namer
Diffstat (limited to 'chiselFrontend/src/main')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/UserModule.scala | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/UserModule.scala b/chiselFrontend/src/main/scala/chisel3/core/UserModule.scala index 422760ec..5183f860 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/UserModule.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/UserModule.scala @@ -72,11 +72,13 @@ abstract class UserModule(implicit moduleCompileOptions: CompileOptions) for (id <- getIds) { id match { case id: BaseModule => id.forceName(default=id.desiredName, _namespace) - case id: Data => id.topBinding match { + case id: MemBase[_] => id.forceName(default="_T", _namespace) + case id: Data if id.topBindingOpt.isDefined => id.topBinding match { case OpBinding(_) | MemoryPortBinding(_) | PortBinding(_) | RegBinding(_) | WireBinding(_) => id.forceName(default="_T", _namespace) - case _ => + case _ => // don't name literals } + case id: Data if id.topBindingOpt.isEmpty => // don't name unbound types } id._onModuleClose } |
