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| author | Andrew Waterman | 2018-03-06 20:55:08 -0600 |
|---|---|---|
| committer | GitHub | 2018-03-06 20:55:08 -0600 |
| commit | a4aa3929eb04f21724ae61ff5e45158eed3d0e3b (patch) | |
| tree | ae6e7fa8a763670fe82b54ee17faef28ee7c8d6b /chiselFrontend/src/main | |
| parent | 916938144702e064d5265473a8a7114de9f5ddf1 (diff) | |
Fix SyncReadMem.read; add test (#796)
SyncReadMem.read with an enable signal currently only works in
compatibility mode, where Wires are implicitly initialized to
DontCare. Fix by explicitly assigning DontCare to the Wire.
This might fix #775.
Diffstat (limited to 'chiselFrontend/src/main')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Mem.scala | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala index 3fe78010..c5862974 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala @@ -156,6 +156,7 @@ sealed class SyncReadMem[T <: Data](t: T, n: Int) extends MemBase[T](t, n) { def do_read(addr: UInt, enable: Bool)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = { val a = Wire(UInt()) + a := DontCare var port: Option[T] = None when (enable) { a := addr |