Fix SyncReadMem.read; add test (#796)

SyncReadMem.read with an enable signal currently only works in
compatibility mode, where Wires are implicitly initialized to
DontCare.  Fix by explicitly assigning DontCare to the Wire.

This might fix #775.

2 files changed, 19 insertions, 0 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
index 3fe78010..c5862974 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
@@ -156,6 +156,7 @@ sealed class SyncReadMem[T <: Data](t: T, n: Int) extends MemBase[T](t, n) {
 
   def do_read(addr: UInt, enable: Bool)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = {
     val a = Wire(UInt())
+    a := DontCare
     var port: Option[T] = None
     when (enable) {
       a := addr
diff --git a/src/test/scala/chiselTests/Mem.scala b/src/test/scala/chiselTests/Mem.scala
index 81b5307c..56110d0f 100644
--- a/src/test/scala/chiselTests/Mem.scala
+++ b/src/test/scala/chiselTests/Mem.scala
@@ -19,8 +19,26 @@ class MemVecTester extends BasicTester {
   }
 }
 
+class SyncReadMemTester extends BasicTester {
+  val (cnt, _) = Counter(true.B, 5)
+  val mem = SyncReadMem(2, UInt(2.W))
+  val rdata = mem.read(cnt - 1.U, cnt =/= 0.U)
+
+  switch (cnt) {
+    is (0.U) { mem.write(cnt, 3.U) }
+    is (1.U) { mem.write(cnt, 2.U) }
+    is (2.U) { assert(rdata === 3.U) }
+    is (3.U) { assert(rdata === 2.U) }
+    is (4.U) { stop() }
+  }
+}
+
 class MemorySpec extends ChiselPropSpec {
   property("Mem of Vec should work") {
     assertTesterPasses { new MemVecTester }
   }
+
+  property("SyncReadMem should work") {
+    assertTesterPasses { new SyncReadMemTester }
+  }
 }