From a4aa3929eb04f21724ae61ff5e45158eed3d0e3b Mon Sep 17 00:00:00 2001
From: Andrew Waterman
Date: Tue, 6 Mar 2018 20:55:08 -0600
Subject: Fix SyncReadMem.read; add test (#796)

SyncReadMem.read with an enable signal currently only works in
compatibility mode, where Wires are implicitly initialized to
DontCare.  Fix by explicitly assigning DontCare to the Wire.

This might fix #775.---
 chiselFrontend/src/main/scala/chisel3/core/Mem.scala | 1 +
 1 file changed, 1 insertion(+)

(limited to 'chiselFrontend/src/main')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
index 3fe78010..c5862974 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
@@ -156,6 +156,7 @@ sealed class SyncReadMem[T <: Data](t: T, n: Int) extends MemBase[T](t, n) {
 
   def do_read(addr: UInt, enable: Bool)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = {
     val a = Wire(UInt())
+    a := DontCare
     var port: Option[T] = None
     when (enable) {
       a := addr
-- 
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