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authorAndrew Waterman2018-05-24 11:46:32 -0700
committerGitHub2018-05-24 11:46:32 -0700
commitbffc8b9e851af88128f1c683e67634ebde25c14b (patch)
tree487471aab617aea14c47d3fea71d2cb2950c128f /chiselFrontend/src/main
parentf10c95aa4ea2e1a7484a9e1629b006322ee0e753 (diff)
Fix UIntToOH for output widths larger than 2^(input width) (#823)
* Add test for UIntToOH * Pad UIntToOH inputs to support oversized output widthds * Optimize Bits.pad in case of known widths * Add missing import and fix test in OneHotMuxSpec
Diffstat (limited to 'chiselFrontend/src/main')
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Bits.scala6
1 files changed, 4 insertions, 2 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index 51f5f5ec..b3091db3 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -190,8 +190,10 @@ sealed abstract class Bits(width: Width, override val litArg: Option[LitArg])
*/
final def pad(that: Int): this.type = macro SourceInfoTransform.thatArg
- def do_pad(that: Int)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): this.type =
- binop(sourceInfo, cloneTypeWidth(this.width max Width(that)), PadOp, that)
+ def do_pad(that: Int)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): this.type = this.width match {
+ case KnownWidth(w) if w >= that => this
+ case _ => binop(sourceInfo, cloneTypeWidth(this.width max Width(that)), PadOp, that)
+ }
/** Returns this wire bitwise-inverted. */
final def unary_~ (): Bits = macro SourceInfoWhiteboxTransform.noArg