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Change of FIRRTL semantics!
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Assignments to a register are no longer affected by enclosing when
statements:
when p :
reg r : UInt,clk,reset
r := a
will lower to:
reg r : UInt,clk,reset
r := a
instead of:
reg r : UInt,clk,reset
when p : r := a
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catching of initialization of accessors. Missing use case of accessing an accessor. Still need to update tests to pass
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conditional assignment
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Updated tests to match. #29.
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extract, not >>
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an optimization that eliminated some when statements.
Added test case.
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invalid <> assignments.
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indexed. Fixed various broken tests.
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tests. Made more tests pass
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smem. Added firrtl-gensym utility to generate a hashmap of names
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instead of using nodes. Added a renaming pass for different backends. This will likely get deprecated, as a more robust name mangling scheme could be needed
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strict. Have not tested this
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reasonable verilog. Requires inlining, future versions will instantiate modules
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flexible, and the output is usually the max of the inputs. Removed all u/s variants, which need to be dealt with in backends where it matters
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plugging in other backends. Also updated a lot of tests, but not all of them because its annoying.
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Should show up with check passes
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isn't duplicated for all the whens
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chisel3/ModuleVec.fir doesn't work because incorrecly generated?
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Conflicts:
TODO
src/main/stanza/passes.stanza
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