sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Expand)	Author
2016-08-15	Remove stanza (#231)	Adam Izraelevitz
2016-02-24	Fixed printf bugs in scala and stanza versions. Required special casing print...	Adam Izraelevitz
2016-02-08	Escape quotes in strings before emitting as Verilog	Palmer Dabbelt
2016-01-28	Fixed rdwr and wr to verilog tests	azidar
2016-01-28	Added tests for previous commit	azidar
2016-01-28	Updated all tests to pass	azidar
2016-01-27	Fixed additional tests and inferring rdwr ports in chirrtl	jackkoenig
2016-01-25	Changed tests to pass with change to postfix of generated name	azidar
2016-01-24	Fixed tests that broke from changing verilog backend and removing mask from w...	azidar
2016-01-16	WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit roadbl...	azidar
2016-01-16	WIP. Compiles and almost done with verilog backend. Need to think about emitt...	azidar
2016-01-16	WIP	azidar
2016-01-16	WIP need to correctly output readwrite ports	azidar
2015-08-28	Moved check type and check kind after check gender	azidar
2015-08-19	Fixed width inference bug where constraints were propagating backwards.	azidar
2015-08-17	Added tests for shl and mem. Fixed bug in verilog output of mem size.	azidar
2015-07-31	Updated tests to pipe from stderr to stdout	azidar
2015-07-14	Added tests for clocks. Added remove scope and special chars passes. Added te...	azidar
2015-06-12	Major revisions to spec. Bumped to v0.1.2	azidar
2015-05-18	First pass at a Verilog Backend. Not tested, but compiles and generates reaso...	azidar