diff options
| author | azidar | 2015-06-12 14:47:54 -0700 |
|---|---|---|
| committer | azidar | 2015-06-12 14:47:54 -0700 |
| commit | a1141295b939f2066186c96791bfd64e19209478 (patch) | |
| tree | 9cf27bcd29797645eba98f24b352141ff11b0264 /test/passes/to-verilog | |
| parent | 21128c8b346693a88b5d8765012c4a7de854a94f (diff) | |
Major revisions to spec. Bumped to v0.1.2
Diffstat (limited to 'test/passes/to-verilog')
| -rw-r--r-- | test/passes/to-verilog/gcd.fir | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/test/passes/to-verilog/gcd.fir b/test/passes/to-verilog/gcd.fir index 170e7866..23a2d4f5 100644 --- a/test/passes/to-verilog/gcd.fir +++ b/test/passes/to-verilog/gcd.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p cw tee %s.out | FileCheck %s ;CHECK: Verilog circuit top : |