diff options
| author | azidar | 2016-01-25 11:29:45 -0800 |
|---|---|---|
| committer | azidar | 2016-01-25 11:29:45 -0800 |
| commit | f6ea3dc1bb5efb4455fd3b995ced36add85a44c0 (patch) | |
| tree | dbc0135e3a4ef0ac387fa9fe02b6f7bba2d4dbe5 /test/passes/to-verilog | |
| parent | a637f4f0cedadf5e81fc9d9d3b1392daf99db603 (diff) | |
Changed tests to pass with change to postfix of generated name
Diffstat (limited to 'test/passes/to-verilog')
| -rw-r--r-- | test/passes/to-verilog/rd-mem.fir | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/test/passes/to-verilog/rd-mem.fir b/test/passes/to-verilog/rd-mem.fir index 909b034b..59829777 100644 --- a/test/passes/to-verilog/rd-mem.fir +++ b/test/passes/to-verilog/rd-mem.fir @@ -29,13 +29,13 @@ circuit top : ;CHECK: wire [1:0] m_c_addr; ;CHECK: wire m_c_en; ;CHECK: wire m_c_clk; -;CHECK: reg [1:0] GEN; +;CHECK: reg [1:0] GEN_0; ;CHECK: reg GEN_1; ;CHECK: assign rdata = m_c_data; ;CHECK: assign m_c_addr = index; ;CHECK: assign m_c_en = ren; ;CHECK: assign m_c_clk = clk; -;CHECK: assign m_c_data = m[GEN]; +;CHECK: assign m_c_data = m[GEN_0]; ;CHECK: `ifndef SYNTHESIS ;CHECK: integer initvar; ;CHECK: initial begin @@ -45,7 +45,7 @@ circuit top : ;CHECK: end ;CHECK: `endif ;CHECK: always @(posedge m_c_clk) begin -;CHECK: GEN <= m_c_addr; +;CHECK: GEN_0 <= m_c_addr; ;CHECK: GEN_1 <= m_c_en; ;CHECK: end ;CHECK: endmodule |