diff options
| -rw-r--r-- | test/passes/lower-to-ground/bundle-vecs.fir | 6 | ||||
| -rw-r--r-- | test/passes/remove-accesses/bundle-vecs.fir | 8 | ||||
| -rw-r--r-- | test/passes/remove-accesses/simple3.fir | 8 | ||||
| -rw-r--r-- | test/passes/remove-accesses/simple4.fir | 6 | ||||
| -rw-r--r-- | test/passes/remove-accesses/simple5.fir | 6 | ||||
| -rw-r--r-- | test/passes/split-exp/split-in-when.fir | 4 | ||||
| -rw-r--r-- | test/passes/to-verilog/rd-mem.fir | 6 |
7 files changed, 22 insertions, 22 deletions
diff --git a/test/passes/lower-to-ground/bundle-vecs.fir b/test/passes/lower-to-ground/bundle-vecs.fir index 9821f69b..64a4a4b6 100644 --- a/test/passes/lower-to-ground/bundle-vecs.fir +++ b/test/passes/lower-to-ground/bundle-vecs.fir @@ -19,11 +19,11 @@ circuit top : j <= a[i] a[i] <= j -;CHECK: wire GEN : UInt<32> +;CHECK: wire GEN_0 : UInt<32> ;CHECK: wire GEN_1 : UInt<32> ;CHECK: wire GEN_2 : UInt<32> ;CHECK: wire GEN_3 : UInt<32> -;CHECK: j_x <= GEN +;CHECK: j_x <= GEN_0 ;CHECK: j_y <= GEN_3 ;CHECK: node GEN_4 = eqv(UInt("h0"), i) ;CHECK: a_0_x <= mux(GEN_4, GEN_2, UInt("h0")) @@ -34,7 +34,7 @@ circuit top : ;CHECK: node GEN_7 = eqv(UInt("h1"), i) ;CHECK: a_1_y <= mux(GEN_7, GEN_1, UInt("h0")) ;CHECK: node GEN_8 = eqv(UInt("h1"), i) -;CHECK: GEN <= mux(GEN_8, a_1_x, a_0_x) +;CHECK: GEN_0 <= mux(GEN_8, a_1_x, a_0_x) ;CHECK: GEN_1 <= j_y ;CHECK: GEN_2 <= j_x ;CHECK: node GEN_9 = eqv(UInt("h1"), i) diff --git a/test/passes/remove-accesses/bundle-vecs.fir b/test/passes/remove-accesses/bundle-vecs.fir index 13f9d8d6..e916bfa8 100644 --- a/test/passes/remove-accesses/bundle-vecs.fir +++ b/test/passes/remove-accesses/bundle-vecs.fir @@ -29,10 +29,10 @@ circuit top : ; CHECK: a[1].x <= UInt("h1") ; CHECK: a[1].y <= UInt("h1") ; CHECK: wire b : { x : UInt<32>, flip y : UInt<32>} -; CHECK: wire GEN : UInt<32> -; CHECK: GEN <= a[0].x -; CHECK: when eqv(UInt("h1"), i) : GEN <= a[1].x -; CHECK: b.x <= GEN +; CHECK: wire GEN_0 : UInt<32> +; CHECK: GEN_0 <= a[0].x +; CHECK: when eqv(UInt("h1"), i) : GEN_0 <= a[1].x +; CHECK: b.x <= GEN_0 ; CHECK: wire GEN_1 : UInt<32> ; CHECK: when eqv(UInt("h0"), i) : a[0].y <= GEN_1 ; CHECK: when eqv(UInt("h1"), i) : a[1].y <= GEN_1 diff --git a/test/passes/remove-accesses/simple3.fir b/test/passes/remove-accesses/simple3.fir index c7d00aff..b19c4130 100644 --- a/test/passes/remove-accesses/simple3.fir +++ b/test/passes/remove-accesses/simple3.fir @@ -12,10 +12,10 @@ circuit top : m[i] <= a a <= in -;CHECK: wire GEN : UInt<32> -;CHECK: when eqv(UInt("h0"), i) : m[0] <= GEN -;CHECK: when eqv(UInt("h1"), i) : m[1] <= GEN -;CHECK: GEN <= a +;CHECK: wire GEN_0 : UInt<32> +;CHECK: when eqv(UInt("h0"), i) : m[0] <= GEN_0 +;CHECK: when eqv(UInt("h1"), i) : m[1] <= GEN_0 +;CHECK: GEN_0 <= a ;CHECK: Finished Remove Accesses diff --git a/test/passes/remove-accesses/simple4.fir b/test/passes/remove-accesses/simple4.fir index 4772c549..06ff7481 100644 --- a/test/passes/remove-accesses/simple4.fir +++ b/test/passes/remove-accesses/simple4.fir @@ -12,9 +12,9 @@ circuit top : m[1].y <= UInt("h1") m[i].x <= in.x -;CHECK: when eqv(UInt("h0"), i) : m[0].x <= GEN -;CHECK: when eqv(UInt("h1"), i) : m[1].x <= GEN -;CHECK: GEN <= in +;CHECK: when eqv(UInt("h0"), i) : m[0].x <= GEN_0 +;CHECK: when eqv(UInt("h1"), i) : m[1].x <= GEN_0 +;CHECK: GEN_0 <= in ;CHECK: Finished Remove Accesses ;CHECK: Done! diff --git a/test/passes/remove-accesses/simple5.fir b/test/passes/remove-accesses/simple5.fir index 099f020c..0a1baed6 100644 --- a/test/passes/remove-accesses/simple5.fir +++ b/test/passes/remove-accesses/simple5.fir @@ -14,8 +14,8 @@ circuit top : o <= m[i] ;CHECK: when i : -;CHECK: GEN <= m[0] -;CHECK: when eqv(UInt("h1"), i) : GEN <= m[1] -;CHECK: o <= GEN +;CHECK: GEN_0 <= m[0] +;CHECK: when eqv(UInt("h1"), i) : GEN_0 <= m[1] +;CHECK: o <= GEN_0 ;CHECK: Finished Remove Accesses ;CHECK: Done! diff --git a/test/passes/split-exp/split-in-when.fir b/test/passes/split-exp/split-in-when.fir index 69e2b96e..e4d0da36 100644 --- a/test/passes/split-exp/split-in-when.fir +++ b/test/passes/split-exp/split-in-when.fir @@ -13,8 +13,8 @@ circuit Top : when bit(subw(a,c),3) : out <= mux(eqv(bits(UInt(32),4,0),UInt(13)),addw(a,addw(b,c)),subw(c,b)) -;CHECK: node GEN = subw(a, c) -;CHECK: node GEN_1 = bit(GEN, 3) +;CHECK: node GEN_0 = subw(a, c) +;CHECK: node GEN_1 = bit(GEN_0, 3) ;CHECK: node GEN_2 = eqv(UInt("h0"), UInt("hd")) ;CHECK: node GEN_3 = addw(b, c) ;CHECK: node GEN_4 = addw(a, GEN_3) diff --git a/test/passes/to-verilog/rd-mem.fir b/test/passes/to-verilog/rd-mem.fir index 909b034b..59829777 100644 --- a/test/passes/to-verilog/rd-mem.fir +++ b/test/passes/to-verilog/rd-mem.fir @@ -29,13 +29,13 @@ circuit top : ;CHECK: wire [1:0] m_c_addr; ;CHECK: wire m_c_en; ;CHECK: wire m_c_clk; -;CHECK: reg [1:0] GEN; +;CHECK: reg [1:0] GEN_0; ;CHECK: reg GEN_1; ;CHECK: assign rdata = m_c_data; ;CHECK: assign m_c_addr = index; ;CHECK: assign m_c_en = ren; ;CHECK: assign m_c_clk = clk; -;CHECK: assign m_c_data = m[GEN]; +;CHECK: assign m_c_data = m[GEN_0]; ;CHECK: `ifndef SYNTHESIS ;CHECK: integer initvar; ;CHECK: initial begin @@ -45,7 +45,7 @@ circuit top : ;CHECK: end ;CHECK: `endif ;CHECK: always @(posedge m_c_clk) begin -;CHECK: GEN <= m_c_addr; +;CHECK: GEN_0 <= m_c_addr; ;CHECK: GEN_1 <= m_c_en; ;CHECK: end ;CHECK: endmodule |