sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Collapse)	Author
2016-08-15	Remove stanza (#231)	Adam Izraelevitz
	* Removed stanza implementation/tests. In the future we can move the stanza tests over, but for now they should be deleted. * Added back integration .fir files * Added Makefile to give Travis hooks * Added firrtl script (was ignored before)
2016-02-09	Changed stanza output of UInt/SInt to include widths. Made tests match ↵	azidar
	accordingly
2016-01-28	Added addw to working ir as an optimized verilog emission	azidar

2016-01-28	Updated all tests to pass	azidar

2016-01-25	Changed tests to pass with change to postfix of generated name	azidar

2016-01-16	Fixed all tests so they either pass are marked as expected failures	azidar

2016-01-16	Fixed a bunch of tests, and minor bugs	azidar

2016-01-16	WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit ↵	azidar
	roadblock in assigning clocked ports
2016-01-16	New memory works with verilog. Slowly changing tests and fixing bugs.	azidar
	Decided to not have Conditionally in low firrtl - instead, Print and Stop have enables
2015-09-30	Fixed naming bug where __1 was matching. Caused lots o issues.	azidar

2015-08-25	Fixed bug in split expression that leaked connect statements out of a ↵	azidar
	conditional assignment