diff options
| author | azidar | 2015-12-09 18:31:45 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:17 -0800 |
| commit | be78d49aa01c097978f69a3b022acb2047fdf438 (patch) | |
| tree | 76dc4b32b5e6861938404ebb4d124ca5b87d13a5 /test/passes/split-exp/split-in-when.fir | |
| parent | c427b31a1ef8361b643d5f7435aeb42472dfe626 (diff) | |
New memory works with verilog. Slowly changing tests and fixing bugs.
Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables
Diffstat (limited to 'test/passes/split-exp/split-in-when.fir')
| -rw-r--r-- | test/passes/split-exp/split-in-when.fir | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/test/passes/split-exp/split-in-when.fir b/test/passes/split-exp/split-in-when.fir index 58819d22..b72a1d95 100644 --- a/test/passes/split-exp/split-in-when.fir +++ b/test/passes/split-exp/split-in-when.fir @@ -11,13 +11,13 @@ circuit Top : reg out : UInt<10>,clk,p - when bit(subw(a,c),3) : out := mux(eqv(bits(UInt(32),4,0),UInt(13)),addw(a,addw(b,c)),subw(c,b)) + when bit(subw(a,c),3) : out <= mux(eqv(bits(UInt(32),4,0),UInt(13)),addw(a,addw(b,c)),subw(c,b)) ;CHECK: node F = subw(a, c) ;CHECK: node out_1 = eqv(UInt("h0"), UInt("hd")) ;CHECK: node out_3 = addw(b, c) ;CHECK: node out_2 = addw(a, out_3) ;CHECK: node out_4 = subw(c, b) -;CHECK: when bit(F, 3) : out := mux(out_1, out_2, out_4) +;CHECK: when bit(F, 3) : out <= mux(out_1, out_2, out_4) ;CHECK: Finished Split Expressions |