New memory works with verilog. Slowly changing tests and fixing bugs.

Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables

3 files changed, 25 insertions, 25 deletions

diff --git a/test/passes/split-exp/gcd.fir b/test/passes/split-exp/gcd.fir
index 0317d634..1f032c04 100644
--- a/test/passes/split-exp/gcd.fir
+++ b/test/passes/split-exp/gcd.fir
@@ -6,7 +6,7 @@ circuit top :
       input x : UInt
       input y : UInt
       output q : UInt
-      q := subw(x, y)
+      q <= subw(x, y)
    module gcd :
       input clk : Clock
       input reset : UInt<1>
@@ -16,22 +16,22 @@ circuit top :
       output z : UInt<16>
       reg x : UInt,clk,reset
       reg y : UInt,clk,reset
-      onreset x := UInt(0)
-      onreset y := UInt(42)
+      onreset x <= UInt(0)
+      onreset y <= UInt(42)
       when gt(x, y) :
          inst s of subtracter
-         s.x := x
-         s.y := y
-         x := s.q
+         s.x <= x
+         s.y <= y
+         x <= s.q
       else :
          inst s2 of subtracter
-         s2.x := x
-         s2.y := y
-         y := s2.q
+         s2.x <= x
+         s2.y <= y
+         y <= s2.q
       when e :
-         x := a
-         y := b
-      z := x
+         x <= a
+         y <= b
+      z <= x
    module top :
       input clk : Clock
       input reset : UInt<1>
@@ -39,11 +39,11 @@ circuit top :
       input b : UInt<16>
       output z : UInt
       inst i of gcd
-      i.clk := clk
-      i.reset := reset
-      i.a := a
-      i.b := b
-      i.e := UInt(1)
-      z := i.z
+      i.clk <= clk
+      i.reset <= reset
+      i.a <= a
+      i.b <= b
+      i.e <= UInt(1)
+      z <= i.z
 
 ; CHECK: Finished Split Expressions
diff --git a/test/passes/split-exp/primop.fir b/test/passes/split-exp/primop.fir
index b2f0af82..caccf57b 100644
--- a/test/passes/split-exp/primop.fir
+++ b/test/passes/split-exp/primop.fir
@@ -6,15 +6,15 @@ circuit Top :
       output out : UInt<1>
 
       wire m : UInt<1>[3]
-      m[0] := UInt(0)
-      m[1] := UInt(0)
-      m[2] := UInt(0)
+      m[0] <= UInt(0)
+      m[1] <= UInt(0)
+      m[2] <= UInt(0)
 
       wire x : UInt<1>
-      x := not(UInt(1))
+      x <= not(UInt(1))
       infer accessor a = m[x]
       
-      out := a
+      out <= a
 
 
 
diff --git a/test/passes/split-exp/split-in-when.fir b/test/passes/split-exp/split-in-when.fir
index 58819d22..b72a1d95 100644
--- a/test/passes/split-exp/split-in-when.fir
+++ b/test/passes/split-exp/split-in-when.fir
@@ -11,13 +11,13 @@ circuit Top :
       
       reg out : UInt<10>,clk,p
 
-      when bit(subw(a,c),3) : out := mux(eqv(bits(UInt(32),4,0),UInt(13)),addw(a,addw(b,c)),subw(c,b))
+      when bit(subw(a,c),3) : out <= mux(eqv(bits(UInt(32),4,0),UInt(13)),addw(a,addw(b,c)),subw(c,b))
 
 ;CHECK: node F = subw(a, c)
 ;CHECK: node out_1 = eqv(UInt("h0"), UInt("hd"))
 ;CHECK: node out_3 = addw(b, c)
 ;CHECK: node out_2 = addw(a, out_3)
 ;CHECK: node out_4 = subw(c, b)
-;CHECK: when bit(F, 3) : out := mux(out_1, out_2, out_4)   
+;CHECK: when bit(F, 3) : out <= mux(out_1, out_2, out_4)   
 
 ;CHECK: Finished Split Expressions