sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Collapse)	Author
2016-08-15	Remove stanza (#231)	Adam Izraelevitz
	* Removed stanza implementation/tests. In the future we can move the stanza tests over, but for now they should be deleted. * Added back integration .fir files * Added Makefile to give Travis hooks * Added firrtl script (was ignored before)
2016-02-09	Changed stanza output of UInt/SInt to include widths. Made tests match ↵	azidar
	accordingly
2016-01-28	Updated all tests to pass	azidar

2016-01-16	WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit ↵	azidar
	roadblock in assigning clocked ports
2016-01-16	New memory works with verilog. Slowly changing tests and fixing bugs.	azidar
	Decided to not have Conditionally in low firrtl - instead, Print and Stop have enables
2015-09-29	Fixed final bug. All tests pass. Accessors are a go.	azidar

2015-08-24	Changed all tests to use verilog backend.	azidar

2015-07-31	Updated tests to pipe from stderr to stdout	azidar

2015-07-30	Updated lots of tests so they pass. Found one bug in expand whens	azidar

2015-07-14	Added tests for clocks. Added remove scope and special chars passes. Added ↵	azidar
	tests. Made more tests pass
2015-07-14	Pass most tests. The ones that do not pass are not expected to, yet	azidar

2015-05-27	Added sequential memories. mem no longer exists, must declare either cmem or ↵	azidar
	smem. Added firrtl-gensym utility to generate a hashmap of names
2015-05-27	Added external modules. Switched lower firrtl back to wire r; r := Register, ↵	azidar
	instead of using nodes. Added a renaming pass for different backends. This will likely get deprecated, as a more robust name mangling scheme could be needed
2015-05-20	Added Pad pass to flo.stanza, which pads widths to make := and primops ↵	azidar
	strict. Have not tested this
2015-05-18	Big API Change. Pad is no longer supported. Widths of primops can be ↵	azidar
	flexible, and the output is usually the max of the inputs. Removed all u/s variants, which need to be dealt with in backends where it matters
2015-04-28	Instances are now male. Reworked lowering pass to be sane. ↵	azidar
	chisel3/ModuleVec.fir doesn't work because incorrecly generated?
2015-04-23	Added new parser. Fixed all Tests. Added on-reset to parser, but don't ↵	azidar
	correctly handle it in compiler.
2015-04-20	Fixed tests to use new execution arguments. Added and fixed chisel3 bugs	azidar

2015-04-08	Fixed bug in lowering that incorrectly determined genders when subfielded	azidar

2015-03-18	Finished expand accessors and lower to ground	azidar