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2016-08-15Remove stanza (#231)Adam Izraelevitz
* Removed stanza implementation/tests. In the future we can move the stanza tests over, but for now they should be deleted. * Added back integration .fir files * Added Makefile to give Travis hooks * Added firrtl script (was ignored before)
2016-02-09Changed stanza output of UInt/SInt to include widths. Made tests match ↵azidar
accordingly
2016-01-28Added addw to working ir as an optimized verilog emissionazidar
2016-01-28Updated all tests to passazidar
2016-01-25Changed tests to pass with change to postfix of generated nameazidar
2016-01-24Added DefMemory to CInfer Typesazidar
2016-01-16Fixed a bunch of tests, and minor bugsazidar
2016-01-16WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit ↵azidar
roadblock in assigning clocked ports
2016-01-16New memory works with verilog. Slowly changing tests and fixing bugs.azidar
Decided to not have Conditionally in low firrtl - instead, Print and Stop have enables
2015-09-29Fixed final bug. All tests pass. Accessors are a go.azidar
2015-08-24Changed all tests to use verilog backend.azidar
2015-07-31Updated tests to pipe from stderr to stdoutazidar
2015-07-30Updated lots of tests so they pass. Found one bug in expand whensazidar
2015-07-14Added tests for clocks. Added remove scope and special chars passes. Added ↵azidar
tests. Made more tests pass
2015-07-14Pass most tests. The ones that do not pass are not expected to, yetazidar
2015-05-27Added sequential memories. mem no longer exists, must declare either cmem or ↵azidar
smem. Added firrtl-gensym utility to generate a hashmap of names
2015-05-27Added external modules. Switched lower firrtl back to wire r; r := Register, ↵azidar
instead of using nodes. Added a renaming pass for different backends. This will likely get deprecated, as a more robust name mangling scheme could be needed
2015-05-20Added Pad pass to flo.stanza, which pads widths to make := and primops ↵azidar
strict. Have not tested this
2015-05-18Big API Change. Pad is no longer supported. Widths of primops can be ↵azidar
flexible, and the output is usually the max of the inputs. Removed all u/s variants, which need to be dealt with in backends where it matters
2015-05-13Added source indicators from FIRRTL files. Pass in -p i to get them printed. ↵azidar
Should show up with check passes
2015-05-13Updated Spec. Added scoped-reg which exposes on-reset bug. Fixed lowering bugazidar
2015-04-28Instances are now male. Reworked lowering pass to be sane. ↵azidar
chisel3/ModuleVec.fir doesn't work because incorrecly generated?
2015-04-27Added on-resetazidar
2015-04-23Added new parser. Fixed all Tests. Added on-reset to parser, but don't ↵azidar
correctly handle it in compiler.
2015-04-20Fixed tests to use new execution arguments. Added and fixed chisel3 bugsazidar
2015-04-08Fixed bug in lowering that incorrectly determined genders when subfieldedazidar
2015-03-25Finished expand-whens. Removed letrec also, a while agoazidar
2015-03-25Correctly do when expansion, minus enables and outputting lowered formazidar
2015-03-23Finished first two parts of expand-whens pass. Fixed inits by adding ↵azidar
WRegInit and removing Null and initialize-register pass
2015-03-18Finished expand accessors and lower to groundazidar
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