sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Expand)	Author
2016-08-15	Remove stanza (#231)	Adam Izraelevitz
2016-02-09	Changed stanza output of UInt/SInt to include widths. Made tests match accord...	azidar
2016-01-16	WIP getting through tests	azidar
2016-01-16	New memory works with verilog. Slowly changing tests and fixing bugs.	azidar
2015-08-28	Moved check type and check kind after check gender	azidar
2015-08-24	Changed all tests to use verilog backend.	azidar
2015-08-19	Fixed width inference bug where constraints were propagating backwards.	azidar
2015-08-18	Fixed so its length is greater than what it connects to. Changed shr to be e...	azidar
2015-07-31	Updated tests to pipe from stderr to stdout	azidar
2015-07-30	Updated lots of tests so they pass. Found one bug in expand whens	azidar
2015-07-14	Pass most tests. The ones that do not pass are not expected to, yet	azidar
2015-07-14	Still partial commit, many tests pass. Many tests fail.	azidar
2015-05-15	Updated firrtl for its passes to be a bit more modular, and to enable pluggin...	azidar
2015-04-23	Added new parser. Fixed all Tests. Added on-reset to parser, but don't correc...	azidar
2015-04-20	Fixed tests to use new execution arguments. Added and fixed chisel3 bugs	azidar
2015-03-12	Switched bundles from gender to flip	azidar
2015-03-05	Finished part of infer gender, tests not committed	azidar
2015-03-04	Finished infer-types pass	azidar