diff options
| author | azidar | 2016-01-31 12:59:31 -0800 |
|---|---|---|
| committer | azidar | 2016-02-09 18:57:06 -0800 |
| commit | e985d47312458459e9ebe42fe99b5a063c08e637 (patch) | |
| tree | d726c711e86d6e948a220a568dcae0a997629d18 /test/passes/infer-types/bundle.fir | |
| parent | 2bd423fa061fb3e0973fa83e98f2877fd4616746 (diff) | |
Changed stanza output of UInt/SInt to include widths. Made tests match accordingly
Diffstat (limited to 'test/passes/infer-types/bundle.fir')
| -rw-r--r-- | test/passes/infer-types/bundle.fir | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/test/passes/infer-types/bundle.fir b/test/passes/infer-types/bundle.fir index 12cc58b1..0a2d2e4f 100644 --- a/test/passes/infer-types/bundle.fir +++ b/test/passes/infer-types/bundle.fir @@ -26,7 +26,7 @@ circuit top : ;CHECK: node y = z@<t:{ x : UInt, flip y : SInt}>.y@<t:SInt> ;CHECK: wire a : UInt<3>[10]@<t:UInt>@<t:UInt[10]@<t:UInt>> ;CHECK: node b = a@<t:UInt[10]@<t:UInt>>[2]@<t:UInt> -;CHECK: node c = a@<t:UInt[10]@<t:UInt>>[UInt("h3")@<t:UInt>] +;CHECK: node c = a@<t:UInt[10]@<t:UInt>>[UInt<2>("h3")@<t:UInt>] ;CHECK: Finished Infer Types |