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2016-08-15Remove stanza (#231)Adam Izraelevitz
* Removed stanza implementation/tests. In the future we can move the stanza tests over, but for now they should be deleted. * Added back integration .fir files * Added Makefile to give Travis hooks * Added firrtl script (was ignored before)
2016-02-09Changed stanza output of UInt/SInt to include widths. Made tests match ↵azidar
accordingly
2016-01-28Updated all tests to passazidar
2016-01-17BIT-AND, BIT-OR, and BIT-XOR now can accept SInts. Fixed testsazidar
2016-01-16Fixed all tests so they either pass are marked as expected failuresazidar
2016-01-16WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit ↵azidar
roadblock in assigning clocked ports
2016-01-16New memory works with verilog. Slowly changing tests and fixing bugs.azidar
Decided to not have Conditionally in low firrtl - instead, Print and Stop have enables
2015-10-01Merge pull request #43 from ucb-bar/new-semanticsAndrew Waterman
Change of FIRRTL semantics!
2015-10-01Change of FIRRTL semantics!azidar
Assignments to a register are no longer affected by enclosing when statements: when p : reg r : UInt,clk,reset r := a will lower to: reg r : UInt,clk,reset r := a instead of: reg r : UInt,clk,reset when p : r := a
2015-09-30Fixed naming bug where __1 was matching. Caused lots o issues.azidar
2015-08-24Changed all tests to use verilog backend.azidar
2015-08-18Updated shr test so it is an expected passazidar
2015-08-18Fixed so its length is greater than what it connects to. Changed shr to be ↵azidar
extract, not >>
2015-08-17Fixed bug where equality between expressions was incorrect, leading toazidar
an optimization that eliminated some when statements. Added test case.
2015-08-17Added tests for shl and mem. Fixed bug in verilog output of mem size.azidar
2015-07-31Updated tests to pipe from stderr to stdoutazidar
2015-07-30Updated error and feature tests. Fixed bug in detecting incorrect gendersazidar
2015-07-30Updated lots of tests so they pass. Found one bug in expand whensazidar
2015-07-14Added tests for clocks. Added remove scope and special chars passes. Added ↵azidar
tests. Made more tests pass
2015-07-14Still partial commit, many tests pass. Many tests fail.azidar
2015-07-14In progress commitazidar
2015-05-27Added sequential memories. mem no longer exists, must declare either cmem or ↵azidar
smem. Added firrtl-gensym utility to generate a hashmap of names
2015-05-27Added external modules. Switched lower firrtl back to wire r; r := Register, ↵azidar
instead of using nodes. Added a renaming pass for different backends. This will likely get deprecated, as a more robust name mangling scheme could be needed
2015-05-20Added Pad pass to flo.stanza, which pads widths to make := and primops ↵azidar
strict. Have not tested this
2015-05-18Big API Change. Pad is no longer supported. Widths of primops can be ↵azidar
flexible, and the output is usually the max of the inputs. Removed all u/s variants, which need to be dealt with in backends where it matters
2015-05-15Updated firrtl for its passes to be a bit more modular, and to enable ↵azidar
plugging in other backends. Also updated a lot of tests, but not all of them because its annoying.
2015-05-13Updated Spec. Added scoped-reg which exposes on-reset bug. Fixed lowering bugazidar
2015-04-27Added on-resetazidar
2015-04-23Added new parser. Fixed all Tests. Added on-reset to parser, but don't ↵azidar
correctly handle it in compiler.
2015-04-20Fixed tests to use new execution arguments. Added and fixed chisel3 bugsazidar
2015-04-08Finished expand whens. started infer widths. added pdf for people to viewazidar
2015-03-27Corrected register init by adding initialization of registers pass after ↵azidar
lowering. Finished expand-whens. Needs more thorough testing of instances
2015-03-25Finished expand-whens. Removed letrec also, a while agoazidar
2015-03-25Correctly do when expansion, minus enables and outputting lowered formazidar
2015-03-23Finished first two parts of expand-whens pass. Fixed inits by adding ↵azidar
WRegInit and removing Null and initialize-register pass
2015-03-18Finished expand accessors and lower to groundazidar