| Age | Commit message (Expand) | Author |
|---|
| 2016-08-15 | Remove stanza (#231) | Adam Izraelevitz |
| 2016-02-09 | Changed stanza output of UInt/SInt to include widths. Made tests match accord... | azidar |
| 2016-01-28 | Updated all tests to pass | azidar |
| 2016-01-17 | BIT-AND, BIT-OR, and BIT-XOR now can accept SInts. Fixed tests | azidar |
| 2016-01-16 | Fixed all tests so they either pass are marked as expected failures | azidar |
| 2016-01-16 | WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit roadbl... | azidar |
| 2016-01-16 | New memory works with verilog. Slowly changing tests and fixing bugs. | azidar |
| 2015-10-01 | Merge pull request #43 from ucb-bar/new-semantics | Andrew Waterman |
| 2015-10-01 | Change of FIRRTL semantics! | azidar |
| 2015-09-30 | Fixed naming bug where __1 was matching. Caused lots o issues. | azidar |
| 2015-08-24 | Changed all tests to use verilog backend. | azidar |
| 2015-08-18 | Updated shr test so it is an expected pass | azidar |
| 2015-08-18 | Fixed so its length is greater than what it connects to. Changed shr to be e... | azidar |
| 2015-08-17 | Fixed bug where equality between expressions was incorrect, leading to | azidar |
| 2015-08-17 | Added tests for shl and mem. Fixed bug in verilog output of mem size. | azidar |
| 2015-07-31 | Updated tests to pipe from stderr to stdout | azidar |
| 2015-07-30 | Updated error and feature tests. Fixed bug in detecting incorrect genders | azidar |
| 2015-07-30 | Updated lots of tests so they pass. Found one bug in expand whens | azidar |
| 2015-07-14 | Added tests for clocks. Added remove scope and special chars passes. Added te... | azidar |
| 2015-07-14 | Still partial commit, many tests pass. Many tests fail. | azidar |
| 2015-07-14 | In progress commit | azidar |
| 2015-05-27 | Added sequential memories. mem no longer exists, must declare either cmem or ... | azidar |
| 2015-05-27 | Added external modules. Switched lower firrtl back to wire r; r := Register, ... | azidar |
| 2015-05-20 | Added Pad pass to flo.stanza, which pads widths to make := and primops strict... | azidar |
| 2015-05-18 | Big API Change. Pad is no longer supported. Widths of primops can be flexible... | azidar |
| 2015-05-15 | Updated firrtl for its passes to be a bit more modular, and to enable pluggin... | azidar |
| 2015-05-13 | Updated Spec. Added scoped-reg which exposes on-reset bug. Fixed lowering bug | azidar |
| 2015-04-27 | Added on-reset | azidar |
| 2015-04-23 | Added new parser. Fixed all Tests. Added on-reset to parser, but don't correc... | azidar |
| 2015-04-20 | Fixed tests to use new execution arguments. Added and fixed chisel3 bugs | azidar |
| 2015-04-08 | Finished expand whens. started infer widths. added pdf for people to view | azidar |
| 2015-03-27 | Corrected register init by adding initialization of registers pass after lowe... | azidar |
| 2015-03-25 | Finished expand-whens. Removed letrec also, a while ago | azidar |
| 2015-03-25 | Correctly do when expansion, minus enables and outputting lowered form | azidar |
| 2015-03-23 | Finished first two parts of expand-whens pass. Fixed inits by adding WRegInit... | azidar |
| 2015-03-18 | Finished expand accessors and lower to ground | azidar |
