sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Collapse)	Author
2016-01-16	WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit ↵	azidar
	roadblock in assigning clocked ports
2016-01-16	New memory works with verilog. Slowly changing tests and fixing bugs.	azidar
	Decided to not have Conditionally in low firrtl - instead, Print and Stop have enables
2015-10-01	Change of FIRRTL semantics!	azidar
	Assignments to a register are no longer affected by enclosing when statements: when p : reg r : UInt,clk,reset r := a will lower to: reg r : UInt,clk,reset r := a instead of: reg r : UInt,clk,reset when p : r := a
2015-08-24	Changed all tests to use verilog backend.	azidar

2015-07-31	Updated tests to pipe from stderr to stdout	azidar

2015-07-30	Updated lots of tests so they pass. Found one bug in expand whens	azidar

2015-07-14	Added tests for clocks. Added remove scope and special chars passes. Added ↵	azidar
	tests. Made more tests pass
2015-07-14	Still partial commit, many tests pass. Many tests fail.	azidar

2015-07-14	In progress commit	azidar