| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2016-08-15 | Remove stanza (#231) | Adam Izraelevitz | |
| * Removed stanza implementation/tests. In the future we can move the stanza tests over, but for now they should be deleted. * Added back integration .fir files * Added Makefile to give Travis hooks * Added firrtl script (was ignored before) | |||
| 2016-02-09 | Changed stanza output of UInt/SInt to include widths. Made tests match ↵ | azidar | |
| accordingly | |||
| 2016-01-16 | New memory works with verilog. Slowly changing tests and fixing bugs. | azidar | |
| Decided to not have Conditionally in low firrtl - instead, Print and Stop have enables | |||
| 2015-08-17 | Removed leading zeros from UInt constants | azidar | |
 |
index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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