sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Expand)	Author
2016-01-24	Added muxing on passive aggregate types	azidar
2016-01-23	Added prefix checker, now compliant with firrtl spec	azidar
2016-01-17	Added check for uint on access index type	azidar
2016-01-16	Fixed all tests so they either pass are marked as expected failures	azidar
2016-01-16	Fixed a bunch of tests, and minor bugs	azidar
2016-01-16	New memory works with verilog. Slowly changing tests and fixing bugs.	azidar
2016-01-16	WIP. Compiles and almost done with verilog backend. Need to think about emitt...	azidar
2015-10-07	Added Printf and Stop to firrtl. #23 #24.	azidar
2015-10-01	Updated tests for previous change that removed RemoveScope test from the Stan...	azidar
2015-08-26	Fixed bug where firrtl was incorrectly judging the width of a bigint. #36 #37.	azidar
2015-08-25	Fixed bug in split expression that leaked connect statements out of a conditi...	azidar
2015-08-25	Added width check pass with tests. #22.	azidar
2015-08-24	Changed all tests to use verilog backend.	azidar
2015-08-20	Added tests, cleaned up repo	azidar
2015-08-20	Added Poison node. Includes tests. #26.	azidar
2015-08-04	Added verilog keywords to uniquify them	azidar
2015-08-04	Fixed reading from instance's input ports. Fixed unique naming bug.	azidar
2015-08-03	Changed name mangling to use _ as a delin. Fixed bug in checking for	azidar
2015-08-03	Fixed performance bug in Split Expressions. Changed delin for connect indexed...	azidar
2015-07-31	Reading from output ports no longer causes errors	azidar
2015-07-31	Added errors for bulk connects where field names match but types/flips don't	azidar
2015-07-31	Updated tests to pipe from stderr to stdout	azidar
2015-07-30	Added module name to error messages.	azidar
2015-07-30	Updated error and feature tests. Fixed bug in detecting incorrect genders	azidar
2015-07-14	Added tests for clocks. Added remove scope and special chars passes. Added te...	azidar
2015-07-14	Pass most tests. The ones that do not pass are not expected to, yet	azidar
2015-06-02	Added sequential/combinational memories. Started debugging verilog backend. A...	azidar
2015-05-27	Added sequential memories. mem no longer exists, must declare either cmem or ...	azidar
2015-05-26	Added <>. Added additional checks for primops. Added new chisel3 files.	azidar
2015-05-20	Added Pad pass to flo.stanza, which pads widths to make := and primops strict...	azidar
2015-05-05	Added a bunch of tests. In the middle of implementing check kinds and check t...	azidar
2015-05-02	Added a infrastructure for check passes, and wrote a few	azidar