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2015-08-24Removed old chisel3 tests that all failed for syntax reasons. Tests should ↵azidar
now be small examples, categorized by either passes, errors, or features.
2015-07-14Pass most tests. The ones that do not pass are not expected to, yetazidar
2015-06-02Added sequential/combinational memories. Started debugging verilog backend. ↵azidar
Added Long support so UInt(LARGENUMBER) works
2015-05-21Added pad pass, used for flo backendazidar
2015-05-02Now when expanding ConnectFrom/ToIndex, create a node for the index so it ↵azidar
isn't duplicated for all the whens
2015-05-01Fixed performance bug where PlusWidth, MinusWidth, and ExpWidth could be ↵azidar
simplified earlier, and also now have equal? defined so mMaxWidth doesn't blow up during width inference
2015-04-28Instances are now male. Reworked lowering pass to be sane. ↵azidar
chisel3/ModuleVec.fir doesn't work because incorrecly generated?
2015-04-20Fixed tests to use new execution arguments. Added and fixed chisel3 bugsazidar
2015-04-16Updated parser to correctly read empty statementsazidar
2015-04-13new chisel3 testsjackbackrack
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