diff options
| author | azidar | 2015-05-21 13:18:09 -0400 |
|---|---|---|
| committer | azidar | 2015-05-21 13:18:09 -0400 |
| commit | eb125225cb96875f31a9af0db187406782b75223 (patch) | |
| tree | a37566e307424a277a3d2fe229f069cbbcca4ae4 /test/chisel3/Mul.fir | |
| parent | 81905d9fdd0debe8f666658607c2a20728baa86d (diff) | |
Added pad pass, used for flo backend
Diffstat (limited to 'test/chisel3/Mul.fir')
| -rw-r--r-- | test/chisel3/Mul.fir | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/test/chisel3/Mul.fir b/test/chisel3/Mul.fir index 46a8c9b9..fab610b6 100644 --- a/test/chisel3/Mul.fir +++ b/test/chisel3/Mul.fir @@ -1,10 +1,11 @@ -; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s -; CHECK: Done! +; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +;CHECK: Done! + circuit Mul : module Mul : input x : UInt<2> - input y : UInt<2> output z : UInt<4> + input y : UInt<2> wire tbl : UInt<4>[16] tbl[0] := UInt<4>(0) @@ -24,6 +25,6 @@ circuit Mul : tbl[14] := UInt<4>(6) tbl[15] := UInt<4>(9) node T_42 = shl(x, 2) - node T_43 = bit-or(Pad(T_42,?), Pad(y,?)) + node T_43 = bit-or(T_42, y) accessor T_44 = tbl[T_43] - z := Pad(T_44,?) + z := T_44 |