| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2015-08-24 | Removed old chisel3 tests that all failed for syntax reasons. Tests should ↵ | azidar | |
| now be small examples, categorized by either passes, errors, or features. | |||
| 2015-07-30 | Updated lots of tests so they pass. Found one bug in expand whens | azidar | |
| 2015-07-14 | Added clock support | azidar | |
| 2015-07-14 | Pass most tests. The ones that do not pass are not expected to, yet | azidar | |
| 2015-06-04 | Fixed fir files so they correctly compile to verilog! Front-end needs to ↵ | azidar | |
| generate as-SInt instead of convert, always. Added fast build to Makefile | |||
| 2015-06-03 | Fixed verilog backend bugs. Passes ALU. Fails Datapath | azidar | |
| 2015-06-02 | Added sequential/combinational memories. Started debugging verilog backend. ↵ | azidar | |
| Added Long support so UInt(LARGENUMBER) works | |||
| 2015-05-26 | Added <>. Added additional checks for primops. Added new chisel3 files. | azidar | |
 |
index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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