diff options
| author | azidar | 2015-06-04 14:56:18 -0700 |
|---|---|---|
| committer | azidar | 2015-06-04 14:56:18 -0700 |
| commit | 06f57fefe8258c7d8149156db7ca01a66f207a5d (patch) | |
| tree | 2598d83574f3675e42e763c18fbb6793b779c8df /test/chisel3/Core.fir | |
| parent | d86272ca9238c12e80e78938bc1dd5a1dc8532da (diff) | |
Fixed fir files so they correctly compile to verilog! Front-end needs to generate as-SInt instead of convert, always. Added fast build to Makefile
Diffstat (limited to 'test/chisel3/Core.fir')
| -rw-r--r-- | test/chisel3/Core.fir | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/test/chisel3/Core.fir b/test/chisel3/Core.fir index b2062c1d..5c446b3d 100644 --- a/test/chisel3/Core.fir +++ b/test/chisel3/Core.fir @@ -18,8 +18,8 @@ circuit Core : node T_1229 = dshr(A, shamt) node T_1230 = dshl(A, shamt) node T_1231 = bits(T_1230, 31, 0) - node T_1232 = convert(A) - node T_1233 = convert(B) + node T_1232 = as-SInt(A) + node T_1233 = as-SInt(B) node T_1234 = lt(T_1232, T_1233) node T_1235 = as-UInt(T_1234) node T_1236 = lt(A, B) @@ -64,8 +64,8 @@ circuit Core : node eq = eq(rs1, rs2) node neq = bit-not(eq) - node T_1267 = convert(rs1) - node T_1268 = convert(rs2) + node T_1267 = as-SInt(rs1) + node T_1268 = as-SInt(rs2) node lt = lt(T_1267, T_1268) node ge = bit-not(lt) node ltu = lt(rs1, rs2) @@ -120,11 +120,11 @@ circuit Core : input inst : UInt<32> node T_1298 = bits(inst, 31, 20) - node Iimm = convert(T_1298) + node Iimm = as-SInt(T_1298) node T_1299 = bits(inst, 31, 25) node T_1300 = bits(inst, 11, 7) node T_1301 = cat(T_1299, T_1300) - node Simm = convert(T_1301) + node Simm = as-SInt(T_1301) node T_1302 = bit(inst, 31) node T_1303 = bit(inst, 7) node T_1304 = bits(inst, 30, 25) @@ -133,10 +133,10 @@ circuit Core : node T_1307 = cat(T_1305, UInt<1>(0)) node T_1308 = cat(T_1304, T_1307) node T_1309 = cat(T_1306, T_1308) - node Bimm = convert(T_1309) + node Bimm = as-SInt(T_1309) node T_1310 = bits(inst, 31, 12) node T_1311 = cat(T_1310, UInt<12>(0)) - node Uimm = convert(T_1311) + node Uimm = as-SInt(T_1311) node T_1312 = bit(inst, 31) node T_1313 = bits(inst, 19, 12) node T_1314 = bit(inst, 20) @@ -147,10 +147,10 @@ circuit Core : node T_1319 = cat(T_1316, UInt<1>(0)) node T_1320 = cat(T_1315, T_1319) node T_1321 = cat(T_1318, T_1320) - node Jimm = convert(T_1321) + node Jimm = as-SInt(T_1321) node T_1322 = bits(inst, 19, 15) node T_1323 = pad(T_1322, 32) - node Zimm = convert(T_1323) + node Zimm = as-SInt(T_1323) node T_1324 = eq(UInt<3>(3), sel) node T_1325 = mux(T_1324, Jimm, Zimm) node T_1326 = eq(UInt<3>(2), sel) @@ -330,11 +330,11 @@ circuit Core : node loffset = bit-or(T_1409, T_1411) node lshift = dshr(dcache.dout, loffset) node T_1412 = bits(lshift, 15, 0) - node T_1413 = convert(T_1412) + node T_1413 = as-SInt(T_1412) node T_1414 = pad(T_1413, 32) node T_1415 = as-UInt(T_1414) node T_1416 = bits(lshift, 7, 0) - node T_1417 = convert(T_1416) + node T_1417 = as-SInt(T_1416) node T_1418 = pad(T_1417, 32) node T_1419 = as-UInt(T_1418) node T_1420 = bits(lshift, 15, 0) |