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AgeCommit message (Expand)Author
2015-07-02Hopefully fixed stanza so it can correctly compile itselfazidar
2015-07-01Updated TODO.azidar
2015-06-12Major revisions to spec. Bumped to v0.1.2azidar
2015-06-05Added updated stanzaazidar
2015-06-05Commited most recent pdfazidar
2015-06-04Fixed fir files so they correctly compile to verilog! Front-end needs to gene...azidar
2015-06-04Added Adam's changes to stanzaazidar
2015-06-03Fixed verilog backend bugs. Passes ALU. Fails Datapathazidar
2015-06-02Added low firrtl check. Corrected bug in prefix matching in high firrtl checkazidar
2015-06-02Changed Core.fir so dshl wasn't huge. Fixed padding pass to preserve correct ...azidar
2015-06-02Merge branch 'master' of github.com:ucb-bar/firrtlazidar
2015-06-02Added sequential/combinational memories. Started debugging verilog backend. A...azidar
2015-06-02turn off eliminate-temps until improvedjackbackrack
2015-06-02merge + fix trim to use correct bits operandsjackbackrack
2015-05-29fix concat, as-sint, turn off temp-eliminationjackbackrack
2015-05-29Fixed bugs in when-coverage pass. Works but has not been thoroughly testedazidar
2015-05-29Added new stanzaazidar
2015-05-29Added custom pass. Does not correctly run, stanza just spins. Requires debugg...azidar
2015-05-27Added sequential memories. mem no longer exists, must declare either cmem or ...azidar
2015-05-27Added external modules. Switched lower firrtl back to wire r; r := Register, ...azidar
2015-05-26Added <>. Added additional checks for primops. Added new chisel3 files.azidar
2015-05-21fix pad/trim pass and fix bug in bits-select width inferencejackbackrack
2015-05-21Added pad pass, used for flo backendazidar
2015-05-20Merge branch 'master' of github.com:ucb-bar/firrtlazidar
2015-05-20fix writeport emission for flojackbackrack
2015-05-20Added Pad pass to flo.stanza, which pads widths to make := and primops strict...azidar
2015-05-19Merge pull request #8 from jackbackrack/masterAdam Izraelevitz
2015-05-19mergejackbackrack
2015-05-19get flo backend running again with no pads and generic operatorsjackbackrack
2015-05-19Added support for non-inlined modules in verilog backendazidar
2015-05-18get coercion running for flo backend and disable negative lit checkjackbackrack
2015-05-18First pass at a Verilog Backend. Not tested, but compiles and generates reaso...azidar
2015-05-18Big API Change. Pad is no longer supported. Widths of primops can be flexible...azidar
2015-05-15Updated firrtl for its passes to be a bit more modular, and to enable pluggin...azidar
2015-05-14mergejackbackrack
2015-05-13Added source indicators from FIRRTL files. Pass in -p i to get them printed. ...azidar
2015-05-13Updated Spec. Added scoped-reg which exposes on-reset bug. Fixed lowering bugazidar
2015-05-07do signed padding as welljackbackrack
2015-05-05Added a bunch of tests. In the middle of implementing check kinds and check t...azidar
2015-05-04mergejackbackrack
2015-05-04Added new stanzaazidar
2015-05-04Fixed bug where instance types were not loweredazidar
2015-05-04mergejackbackrack
2015-05-04Merge branch 'master' of github.com:ucb-bar/firrtlazidar
2015-05-04Updated stuffazidar
2015-05-04add reduction operatorsjackbackrack
2015-05-04Merge pull request #6 from jackbackrack/masterAdam Izraelevitz
2015-05-04Added a few more error checks. Not tested yet. Fixed bug in pad type inferenceazidar
2015-05-04mergejackbackrack
2015-05-04Fixed change where type of mux-ss was incorrectazidar
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