Merge branch 'master' of github.com:ucb-bar/firrtl

3 files changed, 53 insertions, 32 deletions

diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza
index 5a2e2278..9f8959ad 100644
--- a/src/main/stanza/compilers.stanza
+++ b/src/main/stanza/compilers.stanza
@@ -13,7 +13,7 @@ public defstruct StandardFlo <: Compiler :
 public defmethod passes (c:StandardFlo) -> List<Pass> :
    to-list $ [
       CheckHighForm(expand-delin)
-      TempElimination()
+      ;; TempElimination()
       ToWorkingIR()
       MakeExplicitReset()
       ResolveKinds()
@@ -42,7 +42,7 @@ public defstruct StandardVerilog <: Compiler :
 public defmethod passes (c:StandardVerilog) -> List<Pass> :
    to-list $ [
       CheckHighForm(expand-delin)
-      TempElimination()
+      ;; TempElimination()
       ToWorkingIR()
       MakeExplicitReset()
       ResolveKinds()
diff --git a/src/main/stanza/flo.stanza b/src/main/stanza/flo.stanza
index 41de8f82..bb9365ae 100644
--- a/src/main/stanza/flo.stanza
+++ b/src/main/stanza/flo.stanza
@@ -23,43 +23,64 @@ defn set-width (desired:Int,t:Type) -> Type :
       (t) : error("Non-ground type")
 
 defn pad-widths-e (desired:Int,e:Expression) -> Expression :
+   defn trim (desired:Int, e:Expression) :
+     ;; println-all(["TRIM " desired " e " e])
+     DoPrim(BITS-SELECT-OP,list(e),list(desired - 1, 0),set-width(desired,type(e)))
+   defn pad (desired:Int, e:Expression) :
+     ;; println-all(["PAD " desired " e " e])
+     DoPrim(PAD-OP,list(e),list(desired),set-width(desired,type(e)))
+   defn trim-pad (desired:Int, e:Expression) :
+     val i = int-width!(type(e))
+     if i > desired : trim(desired, e)
+     else if i == desired : e
+     else : pad(desired, e)
+   defn self-pad-widths-e (e:Expression) -> Expression :
+     pad-widths-e(int-width!(type(e)), e)
+   ;; println-all(["PAD-E " desired " " e])
    match(e) :
       (e:DoPrim) :
-         println(e)
-         if contains?([ADD-OP,SUB-OP,MUL-OP,DIV-OP,MOD-OP,QUO-OP,REM-OP,ADD-WRAP-OP,SUB-WRAP-OP,MUX-OP,AS-UINT-OP,AS-SINT-OP,DYN-SHIFT-LEFT-OP,DYN-SHIFT-RIGHT-OP,SHIFT-LEFT-OP,SHIFT-RIGHT-OP,NEG-OP,CONVERT-OP,BIT-NOT-OP,BIT-OR-OP,BIT-XOR-OP,BIT-AND-REDUCE-OP,BIT-OR-REDUCE-OP,BIT-XOR-REDUCE-OP],op(e)) : 
-            val e* = map(pad-widths-e{desired,_},e)
-            val i = int-width!(type(e*))
-            if i > desired : 
-               DoPrim(BITS-SELECT-OP,list(e),list(0,desired),set-width(desired,type(e)))
-            else if i == desired : e*
-            else : DoPrim(PAD-OP,list(e*),list(desired),set-width(desired,type(e*)))
-         else : e
-      (e:WRef|WSubfield|WIndex|Register|ReadPort) : 
-         println(e)
-         val i = int-width!(type(e))
-         if i > desired : 
-            DoPrim(BITS-SELECT-OP,list(e),list(0,desired),set-width(desired,type(e)))
-         else if i == desired : e
-         else : DoPrim(PAD-OP,list(e),list(desired),set-width(desired,type(e)))
+         val new-desired = reduce(max, 0, map(int-width!{type(_)}, args(e)))
+         ;; println-all(["  NEW DESIRED " new-desired])
+         val e* =
+           if contains?([CONCAT-OP, DYN-SHIFT-RIGHT-OP, DYN-SHIFT-LEFT-OP], op(e)) :
+             DoPrim(op(e), map(self-pad-widths-e, args(e)), consts(e), type(e))
+           else if contains?([MUX-OP], op(e)) :
+             DoPrim(op(e), list(pad-widths-e(1, args(e)[0]), pad-widths-e(new-desired, args(e)[1]), pad-widths-e(new-desired, args(e)[2])), consts(e), type(e))
+           else :
+             map(pad-widths-e{new-desired,_},e)
+         trim-pad(desired, e*)
+      (e:WRef|WSubfield|WIndex) : 
+         trim-pad(desired, e)
       (e:UIntValue) : 
          val i = int-width!(type(e))
-         if i > desired :
-            DoPrim(BITS-SELECT-OP,list(e),list(0,desired),set-width(desired,type(e)))
+         if i > desired : trim(desired, e)
          else : UIntValue(value(e),IntWidth(desired))
       (e:SIntValue) : 
          val i = int-width!(type(e))
-         if i > desired : 
-            DoPrim(BITS-SELECT-OP,list(e),list(0,desired),set-width(desired,type(e)))
+         if i > desired : trim(desired, e)
          else : SIntValue(value(e),IntWidth(desired))
+      (e:Register) :
+         trim-pad(desired, Register(type(e), pad-widths-e(int-width!(type(e)), value(e)), pad-widths-e(1, enable(e))))
+      (e:ReadPort) :
+         trim-pad(desired, ReadPort(mem(e), self-pad-widths-e(index(e)), type(e), pad-widths-e(1, enable(e))))
+      (e:WritePort) :
+         trim-pad(desired, WritePort(mem(e), self-pad-widths-e(index(e)), type(e), pad-widths-e(1, enable(e))))
       (e) : error(to-string $ e)
 
 defn pad-widths-s (s:Stmt) -> Stmt :
+   ;; println-all(["PAD-S " s])
    match(map(pad-widths-s,s)) :
       (s:Connect) : 
          val i = int-width!(type(loc(s)))
+         val loc* = pad-widths-e(i,loc(s))
          val exp* = pad-widths-e(i,exp(s))
-         Connect(info(s),loc(s),exp*)
-      (s) : s
+         Connect(info(s),loc*,exp*)
+      (s:DefNode) : 
+         val i = int-width!(type(value(s)))
+         val exp* = pad-widths-e(i,value(s))
+         DefNode(info(s),name(s),exp*)
+      (s) :
+         s
 
 public defn pad-widths (c:Circuit) -> Circuit :
    Circuit{info(c),_,main(c)} $
@@ -95,13 +116,14 @@ defn flo-op-name (op:PrimOp, args:List<Expression>) -> String :
       NEQUAL-OP :          "neq"
       EQUAL-OP :           "eq"
       MUX-OP :             "mux"
-      PAD-OP :             if is-sint?(args[0]): "arsh" else: "rsh"
       NEG-OP :             "neg"
       AS-UINT-OP :         "mov"
+      AS-SINT-OP :         "mov"
       SHIFT-LEFT-OP :      "lsh" 
       SHIFT-RIGHT-OP :     if is-sint?(args[0]): "arsh" else: "rsh"
       DYN-SHIFT-LEFT-OP :  "lsh" 
       DYN-SHIFT-RIGHT-OP : if is-sint?(args[0]): "arsh" else: "rsh"
+      PAD-OP :             if is-sint?(args[0]): "arsh" else: "rsh"
       CONVERT-OP :         if is-sint?(args[0]): "arsh" else: "rsh"
       BIT-AND-OP :         "and"
       BIT-NOT-OP :         "not"
@@ -174,14 +196,13 @@ defn emit! (e:Expression,top:Symbol) :
          else if op(e) == BITS-SELECT-OP :
            val w = consts(e)[0] - consts(e)[1] + 1
            emit-all([flo-op-name(op(e), args(e)) "'" w " " args(e)[0] " " consts(e)[1]], top)
-         ;; else if op(e) == CONCAT-OP :
-         ;;   val w = consts(e)[0] - consts(e)[1] + 1
-         ;;   emit-all([flo-op-name(op(e), args(e)) "'" w " " args(e)[0] " " consts(e)[1]], top)
+         else if op(e) == CONCAT-OP :
+           val w = prim-width(type(args(e)[1]))
+           emit-all([flo-op-name(op(e), args(e)) "'" w " " args(e)[0] " " args(e)[1]], top)
+         else if op(e) == PAD-OP or op(e) == CONVERT-OP :
+           emit-all([flo-op-name(op(e), args(e)) "'" prim-width(type(e)) " " args(e)[0] " 0"], top)
          else :
            emit-all([flo-op-name(op(e), args(e)) "'" prim-width(type(e))], top)
-           ;if (op(e) == PAD-U-OP) or (op(e) == PAD-S-OP) :
-             ;emit-all(["  " args(e)[0] " " consts(e)[0]], top)
-           ;else :
            for arg in args(e) do :
              print(" ")
              emit!(arg, top)
diff --git a/src/main/stanza/primop.stanza b/src/main/stanza/primop.stanza
index 7abfa94e..0e343d74 100644
--- a/src/main/stanza/primop.stanza
+++ b/src/main/stanza/primop.stanza
@@ -123,7 +123,7 @@ public defn primop-gen-constraints (e:DoPrim,v:Vector<WGeq>) -> Type :
       BIT-XOR-REDUCE-OP : all-max()
       CONCAT-OP : PlusWidth(width!(args(e)[0]),width!(args(e)[1]))
       BIT-SELECT-OP  : IntWidth(1)
-      BITS-SELECT-OP : IntWidth(consts(e)[0] - consts(e)[1])
+      BITS-SELECT-OP : IntWidth(consts(e)[0] - consts(e)[1] + 1)
 
    match(type(e)) :
       (t:UIntType) : UIntType(w*)