From b84fdd09d1100445a9a8fe7654b842c088ef6ac0 Mon Sep 17 00:00:00 2001 From: jackbackrack Date: Thu, 21 May 2015 23:37:24 -0700 Subject: fix pad/trim pass and fix bug in bits-select width inference --- src/main/stanza/flo.stanza | 68 +++++++++++++++++++++++++++---------------- src/main/stanza/primop.stanza | 2 +- 2 files changed, 44 insertions(+), 26 deletions(-) (limited to 'src') diff --git a/src/main/stanza/flo.stanza b/src/main/stanza/flo.stanza index e870d7ed..c5213a2b 100644 --- a/src/main/stanza/flo.stanza +++ b/src/main/stanza/flo.stanza @@ -23,43 +23,62 @@ defn set-width (desired:Int,t:Type) -> Type : (t) : error("Non-ground type") defn pad-widths-e (desired:Int,e:Expression) -> Expression : + defn trim (desired:Int, e:Expression) : + DoPrim(BITS-SELECT-OP,list(e),list(0,desired),set-width(desired,type(e))) + defn pad (desired:Int, e:Expression) : + DoPrim(PAD-OP,list(e),list(),set-width(desired,type(e))) + defn trim-pad (desired:Int, e:Expression) : + val i = int-width!(type(e)) + if i > desired : trim(desired, e) + else if i == desired : e + else : pad(desired, e) + defn self-pad-widths-e (e:Expression) -> Expression : + pad-widths-e(int-width!(type(e)), e) + ;; println-all(["PAD-E " desired " " e]) match(e) : (e:DoPrim) : - println(e) - if contains?([ADD-OP,SUB-OP,MUL-OP,DIV-OP,MOD-OP,QUO-OP,REM-OP,ADD-WRAP-OP,SUB-WRAP-OP,MUX-OP,AS-UINT-OP,AS-SINT-OP,DYN-SHIFT-LEFT-OP,DYN-SHIFT-RIGHT-OP,SHIFT-LEFT-OP,SHIFT-RIGHT-OP,NEG-OP,CONVERT-OP,BIT-NOT-OP,BIT-OR-OP,BIT-XOR-OP,BIT-AND-REDUCE-OP,BIT-OR-REDUCE-OP,BIT-XOR-REDUCE-OP],op(e)) : - val e* = map(pad-widths-e{desired,_},e) - val i = int-width!(type(e*)) - if i > desired : - DoPrim(BITS-SELECT-OP,list(e),list(0,desired),set-width(desired,type(e))) - else if i == desired : e* - else : DoPrim(PAD-OP,list(e*),list(),set-width(desired,type(e*))) - else : e + val new-desired = reduce(max, 0, map(int-width!{type(_)}, args(e))) + ;; println-all([" NEW DESIRED " new-desired]) + val e* = + if contains?([CONCAT-OP, DYN-SHIFT-RIGHT-OP, DYN-SHIFT-LEFT-OP], op(e)) : + DoPrim(op(e), map(self-pad-widths-e, args(e)), consts(e), type(e)) + else if contains?([MUX-OP], op(e)) : + DoPrim(op(e), list(pad-widths-e(1, args(e)[0]), pad-widths-e(new-desired, args(e)[1]), pad-widths-e(new-desired, args(e)[2])), consts(e), type(e)) + else : + map(pad-widths-e{new-desired,_},e) + trim-pad(desired, e*) (e:WRef|WSubfield|WIndex) : - println(e) - val i = int-width!(type(e)) - if i > desired : - DoPrim(BITS-SELECT-OP,list(e),list(0,desired),set-width(desired,type(e))) - else if i == desired : e - else : DoPrim(PAD-OP,list(e),list(),set-width(desired,type(e))) + trim-pad(desired, e) (e:UIntValue) : val i = int-width!(type(e)) - if i > desired : - DoPrim(BITS-SELECT-OP,list(e),list(0,desired),set-width(desired,type(e))) + if i > desired : trim(desired, e) else : UIntValue(value(e),IntWidth(desired)) (e:SIntValue) : val i = int-width!(type(e)) - if i > desired : - DoPrim(BITS-SELECT-OP,list(e),list(0,desired),set-width(desired,type(e))) + if i > desired : trim(desired, e) else : SIntValue(value(e),IntWidth(desired)) + (e:Register) : + trim-pad(desired, Register(type(e), pad-widths-e(int-width!(type(e)), value(e)), pad-widths-e(1, enable(e)))) + (e:ReadPort) : + trim-pad(desired, ReadPort(mem(e), self-pad-widths-e(index(e)), type(e), pad-widths-e(1, enable(e)))) + (e:WritePort) : + trim-pad(desired, WritePort(mem(e), self-pad-widths-e(index(e)), type(e), pad-widths-e(1, enable(e)))) (e) : error(to-string $ e) defn pad-widths-s (s:Stmt) -> Stmt : + ;; println-all(["PAD-S " s]) match(map(pad-widths-s,s)) : (s:Connect) : val i = int-width!(type(loc(s))) + val loc* = pad-widths-e(i,loc(s)) val exp* = pad-widths-e(i,exp(s)) - Connect(info(s),loc(s),exp*) - (s) : s + Connect(info(s),loc*,exp*) + (s:DefNode) : + val i = int-width!(type(value(s))) + val exp* = pad-widths-e(i,value(s)) + DefNode(info(s),name(s),exp*) + (s) : + s public defn pad-widths (c:Circuit) -> Circuit : Circuit{info(c),_,main(c)} $ @@ -93,13 +112,13 @@ defn flo-op-name (op:PrimOp, args:List) -> String : NEQUAL-OP : "neq" EQUAL-OP : "eq" MUX-OP : "mux" - PAD-OP : if is-sint?(args[0]): "arsh" else: "rsh" NEG-OP : "neg" AS-UINT-OP : "mov" SHIFT-LEFT-OP : "lsh" SHIFT-RIGHT-OP : if is-sint?(args[0]): "arsh" else: "rsh" DYN-SHIFT-LEFT-OP : "lsh" DYN-SHIFT-RIGHT-OP : if is-sint?(args[0]): "arsh" else: "rsh" + PAD-OP : if is-sint?(args[0]): "arsh" else: "rsh" CONVERT-OP : if is-sint?(args[0]): "arsh" else: "rsh" BIT-AND-OP : "and" BIT-NOT-OP : "not" @@ -175,11 +194,10 @@ defn emit! (e:Expression,top:Symbol) : ;; else if op(e) == CONCAT-OP : ;; val w = consts(e)[0] - consts(e)[1] + 1 ;; emit-all([flo-op-name(op(e), args(e)) "'" w " " args(e)[0] " " consts(e)[1]], top) + else if op(e) == PAD-OP or op(e) == CONVERT-OP : + emit-all([flo-op-name(op(e), args(e)) "'" prim-width(type(e)) " " args(e)[0] " 0"], top) else : emit-all([flo-op-name(op(e), args(e)) "'" prim-width(type(e))], top) - ;if (op(e) == PAD-U-OP) or (op(e) == PAD-S-OP) : - ;emit-all([" " args(e)[0] " " consts(e)[0]], top) - ;else : for arg in args(e) do : print(" ") emit!(arg, top) diff --git a/src/main/stanza/primop.stanza b/src/main/stanza/primop.stanza index 023723b8..34ede86c 100644 --- a/src/main/stanza/primop.stanza +++ b/src/main/stanza/primop.stanza @@ -122,7 +122,7 @@ public defn primop-gen-constraints (e:DoPrim,v:Vector) -> Type : BIT-XOR-REDUCE-OP : all-max() CONCAT-OP : PlusWidth(width!(args(e)[0]),width!(args(e)[1])) BIT-SELECT-OP : IntWidth(1) - BITS-SELECT-OP : IntWidth(consts(e)[0] - consts(e)[1]) + BITS-SELECT-OP : IntWidth(consts(e)[0] - consts(e)[1] + 1) match(type(e)) : (t:UIntType) : UIntType(w*) -- cgit v1.2.3 From e668a13b285c87678a708a8af5bee2cfa0f7645b Mon Sep 17 00:00:00 2001 From: jackbackrack Date: Fri, 29 May 2015 12:35:51 -0700 Subject: fix concat, as-sint, turn off temp-elimination --- src/main/stanza/compilers.stanza | 4 ++-- src/main/stanza/flo.stanza | 7 ++++--- 2 files changed, 6 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza index 762ed9a8..8b84cc54 100644 --- a/src/main/stanza/compilers.stanza +++ b/src/main/stanza/compilers.stanza @@ -13,7 +13,7 @@ public defstruct StandardFlo <: Compiler : public defmethod passes (c:StandardFlo) -> List : to-list $ [ CheckHighForm() - TempElimination() + ;; TempElimination() ToWorkingIR() MakeExplicitReset() ResolveKinds() @@ -39,7 +39,7 @@ public defstruct StandardVerilog <: Compiler : public defmethod passes (c:StandardVerilog) -> List : to-list $ [ CheckHighForm() - TempElimination() + ;; TempElimination() ToWorkingIR() MakeExplicitReset() ResolveKinds() diff --git a/src/main/stanza/flo.stanza b/src/main/stanza/flo.stanza index c5213a2b..c75071cd 100644 --- a/src/main/stanza/flo.stanza +++ b/src/main/stanza/flo.stanza @@ -114,6 +114,7 @@ defn flo-op-name (op:PrimOp, args:List) -> String : MUX-OP : "mux" NEG-OP : "neg" AS-UINT-OP : "mov" + AS-SINT-OP : "mov" SHIFT-LEFT-OP : "lsh" SHIFT-RIGHT-OP : if is-sint?(args[0]): "arsh" else: "rsh" DYN-SHIFT-LEFT-OP : "lsh" @@ -191,9 +192,9 @@ defn emit! (e:Expression,top:Symbol) : else if op(e) == BITS-SELECT-OP : val w = consts(e)[0] - consts(e)[1] + 1 emit-all([flo-op-name(op(e), args(e)) "'" w " " args(e)[0] " " consts(e)[1]], top) - ;; else if op(e) == CONCAT-OP : - ;; val w = consts(e)[0] - consts(e)[1] + 1 - ;; emit-all([flo-op-name(op(e), args(e)) "'" w " " args(e)[0] " " consts(e)[1]], top) + else if op(e) == CONCAT-OP : + val w = prim-width(type(args(e)[1])) + emit-all([flo-op-name(op(e), args(e)) "'" w " " args(e)[0] " " args(e)[1]], top) else if op(e) == PAD-OP or op(e) == CONVERT-OP : emit-all([flo-op-name(op(e), args(e)) "'" prim-width(type(e)) " " args(e)[0] " 0"], top) else : -- cgit v1.2.3 From e4e6c8cb3e8876aa468497917ecff7ebfff567a4 Mon Sep 17 00:00:00 2001 From: jackbackrack Date: Tue, 2 Jun 2015 08:48:46 -0700 Subject: turn off eliminate-temps until improved --- src/main/stanza/compilers.stanza | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) (limited to 'src') diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza index 0c3978ab..67c6bfeb 100644 --- a/src/main/stanza/compilers.stanza +++ b/src/main/stanza/compilers.stanza @@ -41,13 +41,8 @@ public defstruct StandardVerilog <: Compiler : file: String with: (as-method => true) public defmethod passes (c:StandardVerilog) -> List : to-list $ [ -<<<<<<< HEAD - CheckHighForm() - ;; TempElimination() -======= CheckHighForm(expand-delin) - TempElimination() ->>>>>>> upstream/master + ;; TempElimination() ToWorkingIR() MakeExplicitReset() ResolveKinds() -- cgit v1.2.3