diff options
| author | jackbackrack | 2015-05-29 12:35:51 -0700 |
|---|---|---|
| committer | jackbackrack | 2015-05-29 12:35:51 -0700 |
| commit | e668a13b285c87678a708a8af5bee2cfa0f7645b (patch) | |
| tree | dcddfb4ca081d996a2e7897de7acf245488759d9 /src | |
| parent | b84fdd09d1100445a9a8fe7654b842c088ef6ac0 (diff) | |
fix concat, as-sint, turn off temp-elimination
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/stanza/compilers.stanza | 4 | ||||
| -rw-r--r-- | src/main/stanza/flo.stanza | 7 |
2 files changed, 6 insertions, 5 deletions
diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza index 762ed9a8..8b84cc54 100644 --- a/src/main/stanza/compilers.stanza +++ b/src/main/stanza/compilers.stanza @@ -13,7 +13,7 @@ public defstruct StandardFlo <: Compiler : public defmethod passes (c:StandardFlo) -> List<Pass> : to-list $ [ CheckHighForm() - TempElimination() + ;; TempElimination() ToWorkingIR() MakeExplicitReset() ResolveKinds() @@ -39,7 +39,7 @@ public defstruct StandardVerilog <: Compiler : public defmethod passes (c:StandardVerilog) -> List<Pass> : to-list $ [ CheckHighForm() - TempElimination() + ;; TempElimination() ToWorkingIR() MakeExplicitReset() ResolveKinds() diff --git a/src/main/stanza/flo.stanza b/src/main/stanza/flo.stanza index c5213a2b..c75071cd 100644 --- a/src/main/stanza/flo.stanza +++ b/src/main/stanza/flo.stanza @@ -114,6 +114,7 @@ defn flo-op-name (op:PrimOp, args:List<Expression>) -> String : MUX-OP : "mux" NEG-OP : "neg" AS-UINT-OP : "mov" + AS-SINT-OP : "mov" SHIFT-LEFT-OP : "lsh" SHIFT-RIGHT-OP : if is-sint?(args[0]): "arsh" else: "rsh" DYN-SHIFT-LEFT-OP : "lsh" @@ -191,9 +192,9 @@ defn emit! (e:Expression,top:Symbol) : else if op(e) == BITS-SELECT-OP : val w = consts(e)[0] - consts(e)[1] + 1 emit-all([flo-op-name(op(e), args(e)) "'" w " " args(e)[0] " " consts(e)[1]], top) - ;; else if op(e) == CONCAT-OP : - ;; val w = consts(e)[0] - consts(e)[1] + 1 - ;; emit-all([flo-op-name(op(e), args(e)) "'" w " " args(e)[0] " " consts(e)[1]], top) + else if op(e) == CONCAT-OP : + val w = prim-width(type(args(e)[1])) + emit-all([flo-op-name(op(e), args(e)) "'" w " " args(e)[0] " " args(e)[1]], top) else if op(e) == PAD-OP or op(e) == CONVERT-OP : emit-all([flo-op-name(op(e), args(e)) "'" prim-width(type(e)) " " args(e)[0] " 0"], top) else : |